PIC18F86J90-I/PT Microchip Technology, PIC18F86J90-I/PT Datasheet - Page 279
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PIC18F86J90-I/PT
Manufacturer Part Number
PIC18F86J90-I/PT
Description
IC PIC MCU FLASH 64KB 80-TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F67J90-IPT.pdf
(450 pages)
2.PIC18F67J90-IPT.pdf
(3 pages)
3.PIC18F67J90-IPT.pdf
(10 pages)
4.PIC18F66J90-IPT.pdf
(444 pages)
Specifications of PIC18F86J90-I/PT
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
80-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
Number Of I /o
67
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3923 B
Interface Type
AUSART, EUSART, I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
67
Number Of Timers
4
Operating Supply Voltage
2.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F86J90-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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FIGURE 19-5:
TABLE 19-5:
© 2009 Microchip Technology Inc.
INTCON
PIR3
PIE3
IPR3
RCSTA2
RCREG2
TXSTA2
SPBRG2
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
RX2 (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG2
RC2IF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX2 input. The RCREG2 (Receive Buffer register) is read after the third word
Name
causing the OERR (Overrun) bit to be set.
AUSART Receive Register
AUSART Baud Rate Generator Register
GIE/GIEH PEIE/GIEL TMR0IE
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
—
—
—
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
LCDIF
LCDIE
LCDIP
Bit 6
RX9
TX9
bit 1
RC2IF
RC2IE
RC2IP
SREN
TXEN
Bit 5
bit 7/8
Preliminary
Stop
INT0IE
bit
TX2IE
TX2IP
CREN
SYNC
TX2IF
Bit 4
Word 1
RCREG2
Start
bit
PIC18F87J90 FAMILY
CTMUIF
CTMUIE
CTMUIP
bit 0
ADDEN
RBIE
Bit 3
—
TMR0IF
CCP2IE
CCP2IP
bit 7/8 Stop
CCP2IF
Word 2
RCREG2
BRGH
FERR
Bit 2
bit
CCP1IF
CCP1IE
CCP1IP
INT0IF
Start
OERR
TRMT
Bit 1
bit
RTCCIE
RTCCIP
RTCCIF
bit 7/8
RX9D
TX9D
DS39933C-page 277
RBIF
Bit 0
Stop
bit
on Page
Values
Reset
53
56
56
56
58
58
58
58
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