DSPIC30F3012-30I/P Microchip Technology, DSPIC30F3012-30I/P Datasheet - Page 68
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DSPIC30F3012-30I/P
Manufacturer Part Number
DSPIC30F3012-30I/P
Description
IC DSPIC MCU/DSP 24K 18DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(210 pages)
2.DSPIC30F2011-20ISO.pdf
(6 pages)
3.DSPIC30F2011-20IP.pdf
(26 pages)
4.DSPIC30F3012-20ISO.pdf
(14 pages)
5.DSPIC30F3012-20ISO.pdf
(20 pages)
6.DSPIC30F3014-30IP.pdf
(244 pages)
Specifications of DSPIC30F3012-30I/P
Program Memory Type
FLASH
Program Memory Size
24KB (8K x 24)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
12
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0202 - ADAPTER MPLABICE 18P 300 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F3012-30IP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F3012-30I/P
Manufacturer:
Microchip Technology
Quantity:
1 936
Company:
Part Number:
DSPIC30F3012-30I/P
Manufacturer:
TI
Quantity:
6
Part Number:
DSPIC30F3012-30I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
DSPIC30F3012-30I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F2011/2012/3012/3013
Address Error Trap:
This trap is initiated when any of the following
circumstances occurs:
1.
2.
3.
4.
5.
6.
DS70139G-page 68
Note:
A misaligned data word access is attempted.
A data fetch from our unimplemented data
memory location is attempted.
A data access of an unimplemented program
memory location is attempted.
An instruction fetch from vector space is
attempted.
Execution of a “BRA #literal” instruction or a
“GOTO #literal” instruction, where literal
is an unimplemented program memory address.
Executing instructions after modifying the PC to
point the unimplemented program memory
addresses. The PC may be modified by loading
a value into the stack and executing a RETURN
instruction.
In the MAC class of instructions, wherein
the data space is split into X and Y data
space, unimplemented X space includes
all of Y space, and unimplemented Y
space includes all of X space.
Stack Error Trap:
This trap is initiated under the following conditions:
• The Stack Pointer is loaded with a value which is
• The Stack Pointer is loaded with a value which is
Oscillator Fail Trap:
This trap is initiated if the external oscillator fails and
operation becomes reliant on an internal RC backup.
8.3.2
It is possible that multiple traps can become active
within the same cycle (e.g., a misaligned word stack
write to an overflowed address). In such a case, the
fixed priority shown in
which may require the user to check if other traps are
pending, in order to completely correct the Fault.
Soft traps include exceptions of priority level 8 through
level 11, inclusive. The arithmetic error trap (level 11)
falls into this category of traps.
Hard traps include exceptions of priority level 12
through level 15, inclusive. The address error (level
12), stack error (level 13) and oscillator error (level 14)
traps fall into this category.
Each hard trap that occurs must be acknowledged
before code execution of any type can continue. If a
lower priority hard trap occurs while a higher priority
trap is pending, acknowledged, or is being processed,
a hard trap conflict occurs.
The device is automatically Reset in a hard trap conflict
condition. The TRAPR Status bit (RCON<15>) is set
when the Reset occurs, so that the condition may be
detected in software.
greater than the (user programmable) limit value
written into the SPLIM register (stack overflow).
less than 0x0800 (simple stack underflow).
HARD AND SOFT TRAPS
© 2010 Microchip Technology Inc.
Figure 8-2
is implemented,