PIC18LF2410-I/SO Microchip Technology, PIC18LF2410-I/SO Datasheet - Page 280
![IC MCU FLASH 8KX16 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18LF2410-I/SO
Manufacturer Part Number
PIC18LF2410-I/SO
Description
IC MCU FLASH 8KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18LF2410-ISO.pdf
(376 pages)
2.PIC18LF2410-ISO.pdf
(8 pages)
3.PIC18LF2410-ISO.pdf
(16 pages)
4.PIC18LF2410-ISO.pdf
(6 pages)
5.PIC18LF2410-ISO.pdf
(6 pages)
6.PIC18LF2410-ISO.pdf
(8 pages)
Specifications of PIC18LF2410-I/SO
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
PIC18
No. Of I/o's
25
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Interface
I2C, SPI, USART
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF2410-I/SO
Manufacturer:
TOSHIBA
Quantity:
3 000
- PIC18LF2410-ISO PDF datasheet
- PIC18LF2410-ISO PDF datasheet #2
- PIC18LF2410-ISO PDF datasheet #3
- PIC18LF2410-ISO PDF datasheet #4
- PIC18LF2410-ISO PDF datasheet #5
- PIC18LF2410-ISO PDF datasheet #6
- Current page: 280 of 376
- Download datasheet (7Mb)
PIC18F2X1X/4X1X
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39636D-page 282
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
W
Q1
=
=
Inclusive OR Literal with W
IORLW k
0 ≤ k ≤ 255
(W) .OR. k → W
N, Z
The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed
in W.
1
1
literal ‘k’
IORLW
Read
0000
Q2
9Ah
BFh
1001
35h
Process
Data
Q3
kkkk
Write to W
Q4
kkkk
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
RESULT =
W
RESULT =
W
Q1
=
=
register ‘f’
Inclusive OR W with f
IORWF
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) .OR. (f) → dest
N, Z
Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’
(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
IORWF
Read
0001
Q2
13h
91h
13h
93h
© 2009 Microchip Technology Inc.
RESULT, 0, 1
f {,d {,a}}
00da
Process
Data
Q3
ffff
destination
Write to
Q4
ffff
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