PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet - Page 99
PIC18LF6310-I/PT
Manufacturer Part Number
PIC18LF6310-I/PT
Description
IC PIC MCU FLASH 4KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F6310-IPT.pdf
(412 pages)
2.PIC18F6310-IPT.pdf
(16 pages)
3.PIC18F6310-IPT.pdf
(4 pages)
4.PIC18F6310-IPT.pdf
(28 pages)
5.PIC18F6310-IPT.pdf
(6 pages)
6.PIC18F6310-IPT.pdf
(4 pages)
7.PIC18F8410-IPT.pdf
(404 pages)
Specifications of PIC18LF6310-I/PT
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
54
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
No. Of I/o's
54
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
No. Of Pwm
RoHS Compliant
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF6310-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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8.2.3
Figure 8-3
mode. This mode allows table write operations to
word-wide external memories with byte selection
capability. This generally includes both word-wide
Flash and SRAM devices.
During a TBLWT cycle, the TABLAT data is presented
on the upper and lower byte of the AD<15:0> bus. The
WRH signal is strobed for each write cycle; the WRL
pin is not used. The BA0 or UB/LB signals are used to
select the byte to be written, based on the Least
Significant bit of the TBLPTR register.
FIGURE 8-3:
2010 Microchip Technology Inc.
Note 1:
PIC18F8410
2:
shows an example of 16-Bit Byte Select
16-BIT BYTE SELECT MODE
AD<15:8>
A<19:16>
AD<7:0>
This signal only applies to table writes. See
Demultiplexing is only required when multiple memory devices are accessed.
WRH
WRL
ALE
BA0
OE
UB
I/O
LB
16-BIT BYTE SELECT MODE EXAMPLE
PIC18F6310/6410/8310/8410
373
373
Section 7.1 “Table Reads and Table
A<20:1>
A<20:1>
138
Flash and SRAM devices use different control signal
combinations to implement Byte Select mode. JEDEC
standard Flash memories require that a controller I/O
port pin be connected to the memory’s BYTE/WORD
pin to provide the select signal. They also use the BA0
signal from the controller as a byte address. JEDEC
standard static RAM memories, on the other hand, use
the UB or LB signals to select the byte.
(2)
A<x:1>
A<x:1>
CE
UB
A0
BYTE/WORD
CE
LB
OE
SRAM Memory
Writes”.
Flash Memory
Address Bus
Data Bus
Control Lines
WR
JEDEC Word
JEDEC Word
OE WR
(1)
D<15:0>
D<15:0>
DS39635C-page 99
(1)
D<15:0>
D<15:0>
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