PIC24FJ64GA004-E/PT Microchip Technology, PIC24FJ64GA004-E/PT Datasheet
PIC24FJ64GA004-E/PT
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... PIC24FJ64GA004 Family © 2008 Microchip Technology Inc. Data Sheet 28/44-Pin General Purpose, 16-Bit Flash Microcontrollers Preliminary DS39881C ...
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... PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Microchip Technology Inc. PIC24FJ64GA004 FAMILY Analog Features: • 10-Bit 13-Channel Analog-to-Digital Converter: - 500 ksps conversion rate - Conversion available during Sleep and Idle • Dual Analog Comparators with Programmable Input/Output Configuration Peripheral Features: • Peripheral Pin Select: ...
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... PIC24FJ64GA004 FAMILY Pin Diagrams 28-Pin SPDIP, SSOP, SOIC AN0/V REF AN1/V REF PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0 PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1 AN4/C1IN-/RP2/SDA2/CN6/RB2 AN5/C1IN+/RP3/SCL2/CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/PMA0/RA3 SOSCI/RP4/PMBE/CN1/RB4 SOSCO/T1CK/CN0/PMA1/RA4 PGD3/EMUD3/RP5/ASDA1/CN27/PMD7/RB5 (1) 28-Pin QFN PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0 PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1 AN4/C1IN-/RP2/SDA2/CN6/RB2 AN5/C1IN+/RP3/SCL2/CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/PMA0/RA3 Legend: RPn represents remappable peripheral pins. ...
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... Pin Diagrams (Continued) (1) 44-Pin QFN RP9/SDA1/CN21/PMD3/RB9 RP22/CN18/PMA1/RC6 RP23/CN17/PMA0/RC7 RP24/CN20/PMA5/RC8 RP25/CN19/PMA6/RC9 DISVREG V CAP PGD2/EMUD2/RP10/CN16/PMD2/RB10 PGC2/EMUC2/RP11/CN15/PMD1/RB11 AN12/RP12/CN14/PMD0/RB12 AN11/RP13/CN13/PMRD/RB13 Legend: RPn represents remappable peripheral pins. Note 1: Back pad on QFN devices should be connected to Vss. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 33 SOSCI/RP4/CN1/RB4 1 TDO/PMA8/RA8 OSCO/CLKO/CN29/RA3 3 30 OSCI/CLKI/CN30/RA2 PIC24FJXXGA004 ...
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... PIC24FJ64GA004 FAMILY Pin Diagrams (Continued) 44-Pin TQFP RP9/SDA1/CN21/PMD3/RB9 RP22/CN18/PMA1/RC6 RP23/CN17/PMA0/RC7 RP24/CN20/PMA5/RC8 RP25/CN19/PMA6/RC9 DISVREG V /V CAP DDCORE PGD2/EMUD2/RP10/CN16/PMD2/RB10 PGC2/EMUC2/RP11/CN15/PMD1/RB11 AN12/RP12/CN14/PMD0/RB12 AN11/RP13/CN13/PMRD/RB13 Legend: RPn represents remappable peripheral pins. DS39881C-page SOSCI/RP4/CN1/RB4 32 TDO/PMA8/RA8 2 31 OSCO/CLKO/CN29/RA3 3 30 OSCI/CLKI/CN30/RA2 PIC24FJXXGA004 AN8/RP18/CN10/PMA2/RC2 7 26 AN7/RP17/CN9/RC1 8 25 AN6/RP16/CN8/RC0 9 24 AN5/C1IN+/RP3/SCL2/CN7/RB3 ...
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... Development Support............................................................................................................................................................... 209 25.0 Instruction Set Summary .......................................................................................................................................................... 213 26.0 Electrical Characteristics .......................................................................................................................................................... 221 27.0 Packaging Information.............................................................................................................................................................. 239 Appendix A: Revision History............................................................................................................................................................. 251 Appendix B: Additional Guidance for PIC24FJ64GA004 Family Applications ................................................................................... 252 Index ................................................................................................................................................................................................. 253 The Microchip Web Site ..................................................................................................................................................................... 257 Customer Change Notification Service .............................................................................................................................................. 257 Customer Support .............................................................................................................................................................................. 257 Reader Response ...
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... PIC24FJ64GA004 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...
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... OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC24FJ64GA004 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes using crystals or ceramic resonators. ...
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... C PIC24FJ64GA004 family devices, sorted by function, is shown in Table 1-2. Note that this table shows the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams in the beginning of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first ...
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... TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ64GA004 FAMILY Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels ...
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... PIC24FJ64GA004 FAMILY FIGURE 1-1: PIC24FJ64GA004 FAMILY GENERAL BLOCK DIAGRAM Interrupt Controller PSV & Table Data Access Control Block 23 23 Address Latch Program Memory Data Latch Address Bus Instruction Decode & Control Power-up Timing OSCO/CLKO Timer Generation OSCI/CLKI Oscillator Start-up Timer FRC/LPRC ...
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... TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS Pin Number 28-Pin Function 28-Pin SPDIP/ QFN QFN/TQFP SSOP/SOIC AN0 2 27 AN1 3 28 AN2 4 1 AN3 5 2 AN4 6 3 AN5 7 4 AN6 — — AN7 — — AN8 — — AN9 26 23 AN10 25 22 AN11 ...
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... PIC24FJ64GA004 FAMILY TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin Function 28-Pin SPDIP/ QFN QFN/TQFP SSOP/SOIC CN0 12 9 CN1 11 8 CN2 2 27 CN3 3 28 CN4 4 1 CN5 5 2 CN6 6 3 CN7 7 4 CN8 — — CN9 — — CN10 — ...
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... TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin Function 28-Pin SPDIP/ QFN QFN/TQFP SSOP/SOIC OSCI 9 6 OSCO 10 7 PGC1 5 2 PGD1 4 1 PGC2 22 19 PGD2 21 18 PGC3 14 12 PGD3 15 11 PMA0 10 7 PMA1 12 9 PMA2 — — PMA3 — ...
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... PIC24FJ64GA004 FAMILY TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin Function 28-Pin SPDIP/ QFN QFN/TQFP SSOP/SOIC RA0 2 27 RA1 3 28 RA2 9 6 RA3 10 7 RA4 12 9 RA7 — — RA8 — — RA9 — — RA10 — — RB0 ...
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... TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin Function 28-Pin SPDIP/ QFN QFN/TQFP SSOP/SOIC RP0 4 1 RP1 5 2 RP2 6 3 RP3 7 4 RP4 11 8 RP5 14 11 RP6 15 12 RP7 16 13 RP8 17 14 RP9 18 15 RP10 21 18 RP11 22 19 RP12 ...
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... PIC24FJ64GA004 FAMILY TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin Function 28-Pin SPDIP/ QFN QFN/TQFP SSOP/SOIC T1CK 12 9 TCK 17 14 TDI 21 18 TDO 18 15 TMS 13 DDCAP DDCORE REF REF Legend: TTL = TTL input buffer ANA = Analog level input/output Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared ...
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... Instructions are associated with predefined addressing modes depending upon their functional requirements. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY For most instructions, the core is capable of executing a data (or program data) memory read, a working reg- ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle ...
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... PIC24FJ64GA004 FAMILY FIGURE 2-1: PIC24F CPU CORE BLOCK DIAGRAM PSV & Table Data Access Control Block Interrupt Controller 8 23 PCH 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Address Bus Data Latch 24 Instruction Decode & Control Control Signals to Various Blocks ...
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... W12 W13 W14 W15 22 Registers or bits shadowed for PUSH.S and POP.S instructions. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Program Space Visibility Page Address Register ...
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... PIC24FJ64GA004 FAMILY 2.2 CPU Control Registers REGISTER 2-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 — — — bit 15 (1) (1) R/W-0 R/W-0 R/W-0 (2) (2) (2) IPL2 IPL1 IPL0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ ...
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... Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — ...
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... PIC24FJ64GA004 FAMILY 2.3.2 DIVIDER The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 32-bit signed/16-bit signed divide 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends and the remainder in W1 ...
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... Program Address Space The program address memory PIC24FJ64GA004 family devices is 4M instructions. The space is addressable by a 24-bit value derived FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES PIC24FJ16GA PIC24FJ32GA GOTO Instruction GOTO Instruction Reset Address Reset Address Interrupt Vector Table ...
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... On device Reset, the configuration information is copied into the appropriate Configuration registers. The addresses of the Flash Configuration Word for devices in the PIC24FJ64GA004 family are shown in Table 3-1. Their location in the memory map is shown with the other memory vectors in Figure 3-1. ...
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... Section 3.3.3 “Reading Data From Program Memory Using Program Space Visibility”). FIGURE 3-3: DATA SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES MSB Address 0001h 07FFh ...
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... PIC24FJ64GA004 FAMILY 3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations consequence of byte accessibility, all Effective Address (EA) calculations are internally scaled to step through word-aligned memory. For example, the ...
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... Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881C-page 27 ...
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... PIC24FJ64GA004 FAMILY DS39881C-page 28 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881C-page 29 ...
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... PIC24FJ64GA004 FAMILY DS39881C-page 30 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881C-page 31 ...
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... PIC24FJ64GA004 FAMILY DS39881C-page 32 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881C-page 33 ...
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... PIC24FJ64GA004 FAMILY DS39881C-page 34 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881C-page 35 ...
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... PIC24FJ64GA004 FAMILY DS39881C-page 36 Preliminary © 2008 Microchip Technology Inc. ...
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... PC<22:16> <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 3.3 Interfacing Program and Data Memory Spaces The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space ...
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... PIC24FJ64GA004 FAMILY TABLE 3-25: PROGRAM SPACE ADDRESS CONSTRUCTION Access Access Type Space Instruction Access User (Code Execution) User TBLRD/TBLWT (Byte/Word Read/Write) Configuration Program Space Visibility User (Block Remap/Read) Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG< ...
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... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16> data address. Note that D<15:8>, the ‘phantom’ byte, will always be ‘0’. ...
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... PIC24FJ64GA004 FAMILY 3.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i ...
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... Run-Time Self-Programming (RTSP) • JTAG • Enhanced In-Circuit Serial Programming (Enhanced ICSP) ICSP allows a PIC24FJ64GA004 family device to be serially programmed while in the end application circuit. This is simply done with two lines for the programming clock and programming data (which are named PGCx ...
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... PIC24FJ64GA004 FAMILY 4.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase blocks of eight rows (512 instructions time and to program one row at a time also possible to program single words. The 8-row erase blocks and single row write blocks are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively ...
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... Memory page erase operation (ERASE = operation (ERASE = 0) 0001 = Memory row program operation (ERASE = operation (ERASE = 1) Note 1: All other combinations of NVMOP3:NVMOP0 are unimplemented. 2: Available in ICSP™ mode only. Refer to device programming specification. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — ...
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... PIC24FJ64GA004 FAMILY 4.6.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY The user can program one row of Flash program memory at a time this necessary to erase the 8-row erase block containing the desired row. The general process is: 1. Read eight rows of program (512 instructions) and store in data RAM. ...
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... W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP BTSC NVMCON, #15 BRA $-2 © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY ; ; Initialize NVMCON ; ; Initialize PM Page Boundary SFR ; An example program memory address ; ; ; Write PM low word into program latch ; Write PM high byte into program latch ; ; ; Write PM low word into program latch ...
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... PIC24FJ64GA004 FAMILY 4.6.2 PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY If a Flash location has been erased, it can be pro- grammed using table write instructions to write an instruction word (24-bit) into the write latch. The TBLPAG register is loaded with the 8 Most Significant Bytes of the Flash address. The TBLWTL and TBLWTH ...
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... Illegal Opcode Configuration Mismatch Uninitialized W Register © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets ...
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... PIC24FJ64GA004 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 U-0 TRAPR IOPUWR — bit 15 R/W-0 R/W-0 R/W-0 EXTR SWR SWDTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TRAPR: Trap Reset Flag bit Trap Conflict Reset has occurred ...
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... MCLR COSC Control bits (OSCCON<14:12>) WDTO SWR © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Setting Event 5.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 5-3. Note that the system Reset signal, SYSRST, is released after the POR and PWRT delay times expire ...
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... PIC24FJ64GA004 FAMILY TABLE 5-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS Reset Type Clock Source POR EC, FRC, FRCDIV, LPRC T ECPLL, FRCPLL XT, HS, SOSC XTPLL, HSPLL BOR EC, FRC, FRCDIV, LPRC ECPLL, FRCPLL XT, HS, SOSC XTPLL, HSPLL MCLR Any Clock WDT Any Clock ...
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... FRC oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 5.2.2.1 FSCM Delay for Crystal and PLL Clock Sources When the system clock source is provided by a crystal ...
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... PIC24FJ64GA004 FAMILY NOTES: DS39881C-page 52 Preliminary © 2008 Microchip Technology Inc. ...
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... These are summarized in Table 6-1 and Table 6-2. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 6.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 6-1. Access to the ...
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... PIC24FJ64GA004 FAMILY FIGURE 6-1: PIC24F INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — ...
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... SPI2 Event Timer1 Timer2 Timer3 Timer4 Timer5 UART1 Error UART1 Receiver UART1 Transmitter UART2 Error UART2 Receiver UART2 Transmitter LVD Low-Voltage Detect © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Vector AIVT IVT Address Number Address 13 00002Eh 00012Eh 18 000038h 000138h 67 00009Ah 00019Ah ...
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... PIC24FJ64GA004 FAMILY 6.3 Interrupt Control and Status Registers The PIC24FJ64GA004 family of devices implements a total of 28 registers for the interrupt controller: • INTCON1 • INTCON2 • IFS0 through IFS4 • IEC0 through IEC4 • IPC0 through IPC12, IPC15, IPC16 and IPC18 Global interrupt control functions are controlled from INTCON1 and INTCON2 ...
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... See Register 2-2 for the description of the remaining bit(s) that are not dedicated to interrupt control functions. 2: The IPL3 bit is concatenated with the IPL2:IPL0 bits (SR<7:5>) to form the CPU interrupt priority level. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 NSTDIS — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — U-0 ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 — — AD1IF bit 15 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 ...
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... Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 T5IF T4IF OC4IF R/W-0 ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 R/W-0 — — PMPIF bit 15 R/W-0 R/W-0 R/W-0 IC5IF IC4IF IC3IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 ...
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... Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — U-0 ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ bit 8 ...
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... Interrupt request enabled 0 = Interrupt request not enabled Note 1: If INTxIE = 1, this external interrupt input must be configured to an available RPn pin. See Section 9.4 ”Peripheral Pin Select” for more information. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 U2TXIE U2RXIE INT2IE bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit ...
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... SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — U-0 ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 U-0 — RTCIE — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit ...
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... Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 — T1IP2 T1IP1 bit 15 U-0 R/W-1 R/W-0 — IC1IP2 IC1IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ...
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... IC2IP2:IC2IP0: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 U-0 R/W-1 T2IP0 — OC2IP2 R/W-0 U-0 U-0 IC2IP0 — ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 — U1RXIP2 U1RXIP1 bit 15 U-0 R/W-1 R/W-0 — SPF1IP2 SPF1IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ...
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... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP2:U1TXIP0: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 AD1IP0 — ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 — CNIP2 CNIP1 bit 15 U-0 R/W-1 R/W-0 — MI2C1P2 MI2C1P1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ...
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... Unimplemented: Read as ‘0’ bit 2-0 INT1IP2:INT1IP0: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 — T4IP2 T4IP1 bit 15 U-0 R/W-1 R/W-0 — OC3IP2 OC3IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ...
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... Unimplemented: Read as ‘0’ bit 2-0 T5IP2:T5IP0: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 U-0 R/W-1 U2TXIP0 — U2RXIP2 R/W-0 U-0 R/W-1 INT2IP0 — ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-23: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — SPI2IP2 SPI2IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 ...
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... IC3IP2:IC3IP0: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 U-0 R/W-1 IC5IP0 — IC4IP2 R/W-0 U-0 U-0 IC3IP0 — ...
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... PIC24FJ64GA004 FAMILY REGISTER 6-25: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — OC5IP2 OC5IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 ...
Page 83
... SI2C2P2:SI2C2P0: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 R/W-1 — — MI2C2P2 R/W-0 U-0 U-0 SI2C2P0 — ...
Page 84
... PIC24FJ64GA004 FAMILY REGISTER 6-28: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 ...
Page 85
... U1ERIP2:U1ERIP0: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 U-0 R/W-1 CRCIP0 — U2ERIP2 R/W-0 U-0 U-0 U1ERIP0 — ...
Page 86
... PIC24FJ64GA004 FAMILY REGISTER 6-30: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 ...
Page 87
... RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 6.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR ...
Page 88
... PIC24FJ64GA004 FAMILY NOTES: DS39881C-page 86 Preliminary © 2008 Microchip Technology Inc. ...
Page 89
... For more information, refer to the “PIC24F Family Reference ”Section 6. Oscillator” (DS39700). The oscillator system for PIC24FJ64GA004 family devices has the following features: • A total of four external and internal oscillator options as clock sources, providing 11 different clock modes • On-chip 4x PLL to boost internal operating frequency ...
Page 90
... PIC24FJ64GA004 FAMILY 7.1 CPU Clocking Scheme The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins • Fast Internal RC (FRC) Oscillator • Low-Power Internal RC (LPRC) Oscillator The primary oscillator and FRC sources have the option of using the internal 4x PLL ...
Page 91
... Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY The Clock Divider register (Register 7-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator. ...
Page 92
... PIC24FJ64GA004 FAMILY REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1 Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit ...
Page 93
... Unimplemented: Read as ‘0’ bit 6 Unimplemented: Read as ‘1’ bit 5-0 Unimplemented: Read as ‘0’ Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-1 R/W-0 R/W-0 (1) DOZE0 DOZEN RCDIV2 ...
Page 94
... PIC24FJ64GA004 FAMILY REGISTER 7-3: OSCTUN: FRC Oscillator Tune Register U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — TUN5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 ...
Page 95
... In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY A recommended code sequence for a clock switch includes the following: 1. Disable interrupts during the OSCCON register unlock and write sequence. ...
Page 96
... PIC24FJ64GA004 FAMILY NOTES: DS39881C-page 94 Preliminary © 2008 Microchip Technology Inc. ...
Page 97
... Additional power-saving tips can also be found in Appendix B: “Addi- tional Guidance for PIC24FJ64GA004 Family Applications” of this document. The PIC24FJ64GA004 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power ...
Page 98
... PIC24FJ64GA004 FAMILY 8.2.2 IDLE MODE Idle mode has these features: • The CPU will stop executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 8.4 “ ...
Page 99
... Data Latch Read LAT Read PORT © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled ...
Page 100
... DS39881C-page 98 9.3 Input Change Notification The input change notification function of the I/O ports allows the PIC24FJ64GA004 family of devices to gen- erate interrupt requests to the processor in response to a change of state on selected input pins. This feature is capable of detecting input change of states even in Sleep mode, when the clocks are disabled. Depending ...
Page 101
... C™, change notification inputs, RTCC alarm outputs or peripherals with analog inputs. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY A key difference between pin select and non pin select peripherals is that pin select peripherals are not asso- ciated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used ...
Page 102
... PIC24FJ64GA004 FAMILY TABLE 9-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) Input Name External Interrupt 1 External Interrupt 2 Timer2 External Clock Timer3 External Clock Timer4 External Clock Timer5 External Clock Input Capture 1 Input Capture 2 Input Capture 3 Input Capture 4 Input Capture 5 Output Compare Fault A ...
Page 103
... Control register lock sequence • Continuous state monitoring • Configuration bit remapping lock © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 9.4.4.1 Control Register Lock Under normal operation, writes to the RPINRx and RPORx registers are not allowed. Attempted writes will appear to execute normally, but the contents of the registers will remain unchanged ...
Page 104
... PIC24FJ64GA004 FAMILY 9.4.5 CONSIDERATIONS FOR PERIPHERAL PIN SELECTION The ability to control peripheral pin selection introduces several considerations into application design that could be overlooked. This is particularly true for several common peripherals that are available only as remappable peripherals. The main consideration is that the peripheral pin selects are not available on default pins in the device’ ...
Page 105
... Peripheral Pin Select Registers The PIC24FJ64GA004 family of devices implements a total of 27 registers for remappable peripheral configuration: • Input Remappable Peripheral Registers (14) • Output Remappable Peripheral Registers (13) REGISTER 9-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 U-0 — — — ...
Page 106
... PIC24FJ64GA004 FAMILY REGISTER 9-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 107
... IC4R4:IC4R0: Assign Input Capture 4 (IC4) to the Corresponding RPn Pin bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 IC3R4:IC3R0: Assign Input Capture 3 (IC3) to the Corresponding RPn Pin bits © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-1 R/W-1 R/W-1 IC2R4 IC2R3 IC2R2 ...
Page 108
... PIC24FJ64GA004 FAMILY REGISTER 9-7: RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 109
... U2CTSR4:U2CTSR0: Assign UART2 Clear to Send (U2CTS) to the Corresponding RPn Pin bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 U2RXR4:U2RXR0: Assign UART2 Receive (U2RX) to the Corresponding RPn Pin bits © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-1 R/W-1 R/W-1 U1CTSR4 U1CTSR3 ...
Page 110
... PIC24FJ64GA004 FAMILY REGISTER 9-11: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 111
... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 SS2R4:SS2R0: Assign SPI2 Slave Select Input (SS2IN) to the Corresponding RPn Pin bits © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-1 R/W-1 R/W-1 SCK2R4 SCK2R3 SCK2R2 R/W-1 ...
Page 112
... PIC24FJ64GA004 FAMILY REGISTER 9-15: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 113
... Table 9-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP6R4:RP6R0: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 9-2 for peripheral function numbers) © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 RP5R4 RP5R3 RP5R2 ...
Page 114
... PIC24FJ64GA004 FAMILY REGISTER 9-19: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 115
... Table 9-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R4:RP14R0: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 9-2 for peripheral function numbers) © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 RP13R4 RP13R3 RP13R2 ...
Page 116
... PIC24FJ64GA004 FAMILY REGISTER 9-23: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 117
... RP22R4:RP22R0: Peripheral Output Function is Assigned to RP22 Output Pin bits (see Table 9-2 for peripheral function numbers) Note 1: Bits are only available on the 44-pin devices; otherwise, they read as ‘0’. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 (1) (1) ...
Page 118
... PIC24FJ64GA004 FAMILY REGISTER 9-27: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 119
... T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Figure 10-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS1:TCKPS0 bits. ...
Page 120
... PIC24FJ64GA004 FAMILY REGISTER 10-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘ ...
Page 121
... Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 bit (T2CON<3> or T4CON<3> = 1). 2. ...
Page 122
... PIC24FJ64GA004 FAMILY FIGURE 11-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM T2CK (T4CK) TGATE 1 Set T3IF (T5IF) 0 (3) ADC Event Trigger Equal MSB Reset (1) Read TMR2 (TMR4) (1) Write TMR2 (TMR4) Data Bus<15:0> Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON and T4CON registers ...
Page 123
... Note 1: This peripheral’s inputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin Select” for more information. 2: The ADC event trigger is available only on Timer3. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 1x Gate Sync 01 00 ...
Page 124
... PIC24FJ64GA004 FAMILY REGISTER 11-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timerx On bit When TxCON<3> ...
Page 125
... When 32-bit operation is enabled (T2CON<3> or T4CON<3> = 1), these bits have no effect on Timery operation; all timer functions are set through T2CON and T4CON TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select” for more information. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 (1) — — ...
Page 126
... PIC24FJ64GA004 FAMILY NOTES: DS39881C-page 124 Preliminary © 2008 Microchip Technology Inc. ...
Page 127
... An ‘x’ signal, register or bit name denotes the number of the capture channel. 2: This peripheral’s inputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin Select” for more information. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Manual”, FIFO Edge Detection Logic R/W ...
Page 128
... PIC24FJ64GA004 FAMILY 12.1 Input Capture Registers REGISTER 12-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER U-0 U-0 R/W-0 — — ICSIDL bit 15 R/W-0 R/W-0 R/W-0 ICTMR ICI1 ICI0 bit 7 Legend Hardware Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘ ...
Page 129
... OCxIE bit. For further information on peripheral interrupts, refer to Section 6.0 “Interrupt Controller”. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 10. To initiate another single pulse output, change the Timer and Compare register settings, if needed, and then issue a write to set the OCM bits to ‘100’. ...
Page 130
... PIC24FJ64GA004 FAMILY 13.3 Pulse-Width Modulation Mode Note: This peripheral contains input and output functions that may need to be configured by the peripheral pin Section 9.4 “Peripheral Pin Select” for more information. The following steps should be taken when configuring the output compare module for PWM operation: 1 ...
Page 131
... EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (F PWM Frequency 30.5 Hz Timer Prescaler Ratio 8 Period Register Value FFFFh Resolution (bits) 16 Note 1: Based /2, Doze mode and PLL are disabled. CY OSC © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY • (Timer 2 Prescale Value) /F )/log 2) bits PWM 10 2) bits 122 Hz 977 FFFFh ...
Page 132
... PIC24FJ64GA004 FAMILY FIGURE 13-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM (1) OCxRS (1) OCxR Comparator OCTSEL TMR register inputs from time bases (see Note 3). Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through 5. 2: OCFA pin controls OC1-OC4 channels. OCFB pin controls the OC5 channel. ...
Page 133
... RPORx (OCx) must be configured to an available RPn pin. For more information, see Section 9.4 “Peripheral Pin Select”. 2: OCFA pin controls OC1-OC4 channels. OCFB pin controls the OC5 channel. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — ...
Page 134
... PIC24FJ64GA004 FAMILY NOTES: DS39881C-page 132 Preliminary © 2008 Microchip Technology Inc. ...
Page 135
... Block diagrams of the module in Standard and Enhanced modes are shown in Figure 14-1 and Figure 14-2. Depending on the pin count, devices of the PIC24FJ64GA004 family offer one or two SPI modules on a single device. Note: In this section, the SPI modules are referred to together as SPIx or separately as SPI1 and SPI2 ...
Page 136
... PIC24FJ64GA004 FAMILY To set up the SPI module for the Standard Master mode of operation using interrupts: a) Clear the SPIxIF bit in the respective IFSx register. b) Set the SPIxIE bit in the respective IECx register. c) Write the SPIxIP bits in the respective IPCx register to set the interrupt priority. ...
Page 137
... SPIxSR Transfer 8-Level FIFO Receive Buffer SPIxBUF Read SPIxBUF © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. Clear the SPIxBUF register using interrupts: • Clear the SPIxIF bit in the respective IFSx register. • ...
Page 138
... PIC24FJ64GA004 FAMILY REGISTER 14-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 (1) SPIEN — SPISIDL bit 15 R-0 R/C-0 R/W-0 SRMPT SPIROV SRXMPT bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 SPIEN: SPIx Enable bit ...
Page 139
... Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 9.4 “Peripheral Pin Select” for more information. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881C-page 137 ...
Page 140
... PIC24FJ64GA004 FAMILY REGISTER 14-2: SPI CON1: SPIx CONTROL REGISTER 1 X U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 (4) SSEN CKP MSTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 141
... Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer enabled 0 = Enhanced Buffer disabled (Legacy mode) © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — ...
Page 142
... PIC24FJ64GA004 FAMILY FIGURE 14-3: SPI MASTER/SLAVE CONNECTION (STANDARD MODE) PROCESSOR 1 (SPI Master) Serial Receive Buffer (2) (SPIxRXB) Shift Register (SPIxSR) MSb Serial Transmit Buffer (2) (SPIxTXB) SPIx Buffer (2) (SPIxBUF) MSTEN (SPIxCON1<5> Note 1: Using the SSx pin in Slave mode of operation is optional. 2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF ...
Page 143
... FIGURE 14-7: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Slave) FIGURE 14-8: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PIC24F (SPI Master, Frame Slave) © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY PROCESSOR 2 SDOx SDIx SDIx SDOx Serial Clock SCKx SCKx ...
Page 144
... PIC24FJ64GA004 FAMILY EQUATION 14-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED F SCK Note 1: Based TABLE 14-1: SAMPLE SCK FREQUENCIES MHz CY Primary Prescaler Settings MHz CY Primary Prescaler Settings Note 1: Based /2; Doze mode and PLL are disabled. CY OSC 2: SCKx frequencies shown in kHz. DS39881C-page 142 ...
Page 145
... ASDA1 during device configuration. Pin assignment is controlled by the I2C1SEL Configu- ration bit; programming this bit (= 0) multiplexes the module to the ASCL1 and ASDA1 pins. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 15.2 Communicating as a Master in a Single Master Environment The details of sending a message in Master mode depends on the communications protocol for the device being communicated with ...
Page 146
... PIC24FJ64GA004 FAMILY 2 FIGURE 15-1: I C™ BLOCK DIAGRAM Shift SCLx Clock SDAx Shift Clock BRG Down Counter DS39881C-page 144 I2CxRCV I2CxRSR LSB Address Match Match Detect I2CxADD Start and Stop Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation ...
Page 147
... Address will be Acknowledged only if GCEN = 1. 3: Match on this address can only occur on the upper byte in 10-Bit Addressing mode. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 15.4 Slave Address Masking The I2CxMSK register (Register 15-3) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes ...
Page 148
... PIC24FJ64GA004 FAMILY REGISTER 15-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 I2CEN — I2CSIDL bit 15 R/W-0 R/W-0 R/W-0 GCEN STREN ACKDT bit 7 Legend Hardware Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables I2Cx module ...
Page 149
... SEN: Start Condition Enabled bit (when operating Initiates Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence Start condition not in progress © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 2 C master. Applicable during master receive master. Applicable during master ...
Page 150
... PIC24FJ64GA004 FAMILY REGISTER 15-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 ACKSTAT TRSTAT — bit 15 R/C-0, HS R/C-0, HS R-0, HSC IWCOL I2COV D/A bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ACKSTAT: Acknowledge Status bit ...
Page 151
... TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 2 C slave device address byte. Preliminary DS39881C-page 149 ...
Page 152
... PIC24FJ64GA004 FAMILY REGISTER 15-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-10 Unimplemented: Read as ‘0’ ...
Page 153
... This peripheral’s inputs and outputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin Select” for more information. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY • Fully Integrated Baud Rate Generator with 16-Bit Prescaler • ...
Page 154
... PIC24FJ64GA004 FAMILY 16.1 UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator. The UxBRG register controls the period of a free-running, 16-bit timer. Equation 16-1 shows the formula for computation of the baud rate with BRGH = 0. EQUATION 16-1: ...
Page 155
... FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 16.5 Receiving in 8-Bit or 9-Bit Data Mode 1. Set up the UART (as described in Section 16.2 “Transmitting in 8-Bit Data Mode”). ...
Page 156
... PIC24FJ64GA004 FAMILY REGISTER 16-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 (1) UARTEN — USIDL bit 15 R/C-0, HC R/W-0 R/W-0, HC WAKE LPBACK ABAUD bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 UARTEN: UARTx Enable bit 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> ...
Page 157
... If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select” for more information. 2: This feature is only available for the 16x BRG mode (BRGH = 0). 3: Bit availability depends on pin availability. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881C-page 155 ...
Page 158
... PIC24FJ64GA004 FAMILY REGISTER 16-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 UTXISEL1 UTXINV UTXISEL0 bit 15 R/W-0 R/W-0 R/W-0 URXISEL1 URXISEL0 ADDEN bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15,13 UTXISEL1:UTXISEL0: Transmission Interrupt Mode Selection bits 11 = Reserved ...
Page 159
... Receive buffer has data; at least one more character can be read 0 = Receive buffer is empty Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select” for more information. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881C-page 157 ...
Page 160
... PIC24FJ64GA004 FAMILY REGISTER 16-3: UxTXREG: UARTx TRANSMIT REGISTER U-x U-x U-x — — — bit 15 W-x W-x W-x UTX7 UTX6 UTX5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ bit 8 UTX8: Data of the Transmitted Character bit (in 9-bit mode) ...
Page 161
... Because the interface to parallel peripherals varies significantly, the PMP is highly configurable. Note: A number of the pins for the PMP are not present on PIC24FJ64GA004 devices. Refer to the specific device’s pinout to determine which pins are available. FIGURE 17-1: PMP MODULE OVERVIEW ...
Page 162
... PIC24FJ64GA004 FAMILY REGISTER 17-1: PMCON: PARALLEL PORT CONTROL REGISTER R/W-0 U-0 R/W-0 PMPEN — PSIDL bit 15 R/W-0 R/W-0 R/W-0 CSF1 CSF0 ALP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 PMPEN: Parallel Master Port Enable bit ...
Page 163
... For Master Mode 1 (PMMODE<9:8> Read/write strobe active-high (PMRD/PMWR Read/write strobe active-low (PMRD/PMWR) Note 1: PMA<10:2> are not available on 28-pin devices. 2: These bits have no effect when their corresponding pins are used as address lines. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881C-page 161 ...
Page 164
... PIC24FJ64GA004 FAMILY REGISTER 17-2: PMMODE: Parallel Port Mode Register R-0 R/W-0 R/W-0 BUSY IRQM1 IRQM0 bit 15 R/W-0 R/W-0 R/W-0 (1) (1) WAITB1 WAITB0 WAITM3 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 BUSY: Busy bit (Master mode only) ...
Page 165
... PTEN1:PTEN0: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL 0 = PMA1 and PMA0 pads functions as port I/O Note 1: PMA<10:2> are not available on 28-pin devices. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 — — R/W-0 R/W-0 (1) ADDR< ...
Page 166
... PIC24FJ64GA004 FAMILY REGISTER 17-5: PMSTAT: PARALLEL PORT STATUS REGISTER R-0 R/W-0, HS U-0 IBF IBOV — bit 15 R-1 R/W-0, HS U-0 OBE OBUF — bit 7 Legend Hardware Set bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 IBF: Input Buffer Full Status bit ...
Page 167
... PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL) bit needs to be set. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — ...
Page 168
... PIC24FJ64GA004 FAMILY FIGURE 17-2: LEGACY PARALLEL SLAVE PORT EXAMPLE Master PMD<7:0> PMCS1 PMRD PMWR FIGURE 17-3: ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE Master PMA<1:0> PMD<7:0> PMCS1 PMRD PMWR Address Bus Data Bus Control Lines TABLE 17-1: SLAVE MODE ADDRESS RESOLUTION PMA<1:0> Output Register (Buffer) 00 PMDOUT1< ...
Page 169
... PMALL PMALH PMCS1 PMRD PMWR FIGURE 17-8: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION PIC24F PMD<7:0> PMALL PMA<10:8> PMCS1 PMRD PMWR © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY PMA<10:8> PMD<7:0> PMA<7:0> PMCS1 PMALL PMRD PMWR PMD<7:0> PMA<7:0> PMA<15:8> PMCS1 PMALL PMALH PMRD PMWR A< ...
Page 170
... PIC24FJ64GA004 FAMILY FIGURE 17-9: EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION PIC24F PMD<7:0> PMALL PMCS1 PMRD PMWR FIGURE 17-10: PARALLEL EEPROM EXAMPLE (UP TO 11-BIT ADDRESS, 8-BIT DATA) PIC24F PMA<n:0> PMD<7:0> PMCS1 PMRD PMWR FIGURE 17-11: PARALLEL EEPROM EXAMPLE (UP TO 11-BIT ADDRESS, 16-BIT DATA) PIC24F PMA< ...
Page 171
... Input from SOSC Oscillator RTCC Prescalers RTCC Timer Alarm Event Comparator Compare Registers with Masks Repeat Counter © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Manual”, CPU Clock Domain RCFGCAL ALCFGRPT 0.5s RTCVAL ALRMVAL RTCC Interrupt Logic Preliminary YEAR ...
Page 172
... PIC24FJ64GA004 FAMILY 18.1 RTCC Module Registers The RTCC module registers are organized into three categories: • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers 18.1.1 REGISTER MAPPING To limit the register interface, the RTCC Timer and Alarm Time registers are accessed through corre- sponding register pointers ...
Page 173
... The RCFGCAL register is only affected by a POR write to the RTCEN bit is only allowed when RTCWREN = 1. 3: This bit is read-only cleared to ‘0’ write to the lower half of the MINSEC register. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R-0 R-0 R/W-0 (3) RTCSYNC HALFSEC ...
Page 174
... PIC24FJ64GA004 FAMILY REGISTER 18-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER bit 7-0 CAL7:CAL0: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute ... 01111111 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment 11111111 = Minimum negative adjustment ...
Page 175
... Alarm will repeat 255 more times ... 00000000 = Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFh unless CHIME = 1. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 AMASK2 AMASK1 ...
Page 176
... PIC24FJ64GA004 FAMILY 18.1.4 RTCVAL REGISTER MAPPINGS REGISTER 18-4: YEAR: YEAR VALUE REGISTER U-0 U-0 U-0 — — — bit 15 R/W-x R/W-x R/W-x YRTEN3 YRTEN2 YRTEN1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 Unimplemented: Read as ‘0’ ...
Page 177
... Unimplemented: Read as ‘0’ bit 6-4 SECTEN2:SECTEN0: Binary Coded Decimal Value of Second’s Tens Digit; Contains a value from bit 3-0 SECONE3:SECONE0: Binary Coded Decimal Value of Second’s Ones Digit; Contains a value from © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 R/W-x — — ...
Page 178
... PIC24FJ64GA004 FAMILY 18.1.5 ALRMVAL REGISTER MAPPINGS REGISTER 18-8: ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-x — — DAYTEN1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘ ...
Page 179
... Once the error is known, it must be converted to the number of error clock pulses per minute. EQUATION 18-1: (Ideal Frequency† – Measured Frequency Clocks per Minute † Ideal frequency = 32,768 Hz © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-x R/W-x R/W-x MINTEN0 MINONE3 MINONE2 ...
Page 180
... PIC24FJ64GA004 FAMILY 18.3 Alarm • Configurable from half second to one year • Enabled using the ALRMEN bit (ALCFGRPT<15>, Register 18-3) • One-time alarm and repeat alarm options available 18.3.1 CONFIGURING THE ALARM The alarm feature is enabled using the ALRMEN bit. This bit is cleared when an alarm is issued. Writes to ALRMVAL should only take place when ALRMEN = 0 ...
Page 181
... XOR 0 OUT IN D BIT 0 OUT 1 p_clk © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Consider the CRC equation: To program this polynomial into the CRC generator, the CRC register bits should be set as shown in Table 19-1. TABLE 19-1: Bit Name Manual”, PLEN3:PLEN0 X<15:1> ...
Page 182
... PIC24FJ64GA004 FAMILY FIGURE 19-2: CRC GENERATOR RECONFIGURED FOR x XOR SDOx BIT 0 BIT 4 p_clk p_clk 19.1 User Interface 19.1.1 DATA INTERFACE To start serial shifting, a ‘1’ must be written to the CRCGO bit. The module incorporates a FIFO that is 8 deep when PLEN (PLEN<3:0>) > 7, and 16 deep, otherwise. The data for which the CRC calculated must first be written into the FIFO ...
Page 183
... CRCGO: Start CRC bit 1 = Start CRC serial shifter 0 = CRC serial shifter turned off bit 3-0 PLEN3:PLEN0: Polynomial Length bits Denotes the length of the polynomial to be generated minus 1. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R-0 R-0 R-0 VWORD4 VWORD3 VWORD2 R/W-0 ...
Page 184
... PIC24FJ64GA004 FAMILY REGISTER 19-2: CRCXOR: CRC XOR POLYNOMIAL REGISTER R/W-0 R/W-0 R/W-0 X15 X14 X13 bit 15 R/W-0 R/W-0 R/W bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-1 X15:X1: XOR of Polynomial Term X bit 0 Unimplemented: Read as ‘0’ ...
Page 185
... The actual number of analog input pins and external voltage reference input configuration will depend on the specific device. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY A block diagram of the A/D Converter is shown in Figure 20-1. To perform an A/D conversion: 1 ...
Page 186
... PIC24FJ64GA004 FAMILY FIGURE 20-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM REF REF AN0 V INH AN1 AN2 AN3 AN4 V INL AN5 (1) AN6 (1) AN7 (1) V AN8 AN9 V AN10 AN11 AN12 ( Note 1: Analog channels AN6 through AN8 are available on 28-pin devices only. 2: Band gap voltage reference (V ...
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... SAMP: A/D Sample Enable bit 1 = A/D sample/hold amplifier is sampling input 0 = A/D sample/hold amplifier is holding bit 0 DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is NOT done © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — U-0 ...
Page 188
... PIC24FJ64GA004 FAMILY REGISTER 20-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 VCFG2 VCFG1 VCFG0 bit 15 R-0 U-0 R/W-0 BUFS — SMPI3 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 VCFG2:VCFG0: Voltage Reference Configuration bits VCFG2:VCFG0 ...
Page 189
... AD bit 7-0 ADCS7:ADCS0: A/D Conversion Clock Select bits 11111111 = 256 • ······ 00000001 = 2 • 00000000 = T CY © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 SAMC4 SAMC3 SAMC2 R/W-0 R/W-0 R/W-0 ADCS4 ADCS3 ADCS2 U = Unimplemented bit, read as ‘ ...
Page 190
... PIC24FJ64GA004 FAMILY REGISTER 20-4: AD1CHS: A/D INPUT SELECT REGISTER R/W-0 U-0 U-0 CH0NB — — bit 15 R/W-0 U-0 U-0 CH0NA — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit ...
Page 191
... Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan Note 1: Analog channels AN6, AN7 and AN8 are unavailable on 28-pin devices; leave these corresponding bits cleared. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 PCFG12 PCFG11 ...
Page 192
... PIC24FJ64GA004 FAMILY EQUATION 20-1: A/D CONVERSION CLOCK PERIOD Note 1: Based on T FIGURE 20-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL ANx PIN 6-11 pF (Typical) Legend: C Note: C value depends on device package and is not tested. Effect of C PIN DS39881C-page 190 ( • (ADCS + – 1 ADCS = ...
Page 193
... Voltage Level © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881C-page 191 ...
Page 194
... PIC24FJ64GA004 FAMILY NOTES: DS39881C-page 192 Preliminary © 2008 Microchip Technology Inc. ...
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... C2IN REF Note 1: This peripheral’s outputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin Select” for more information. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Manual”, Compare” C1EN C1INV - C1 + C2EN C2INV ...
Page 196
... PIC24FJ64GA004 FAMILY REGISTER 21-1: CMCON: COMPARATOR CONTROL REGISTER R/W-0 U-0 R/C-0 CMIDL — C2EVT bit 15 R-0 R-0 R/W-0 C2OUT C1OUT C2INV bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 CMIDL: Stop in Idle Mode bit 1 = When device enters Idle mode, module does not generate interrupts; module is still enabled ...
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... If C2OUTEN = 1, the C2OUT peripheral output must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select” for more information C1OUTEN = 1, the C1OUT peripheral output must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select” for more information. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY + ...
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... PIC24FJ64GA004 FAMILY NOTES: DS39881C-page 196 Preliminary © 2008 Microchip Technology Inc. ...
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... CVREN CVRR V - REF © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected (CVR3:CVR0), with one range offering finer resolution. ...
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... PIC24FJ64GA004 FAMILY REGISTER 22-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 Unimplemented: Read as ‘0’ ...