DSPIC30F1010-30I/SO Microchip Technology, DSPIC30F1010-30I/SO Datasheet - Page 15

• Manufacturer Part Number: DSPIC30F1010-30I/SO
• Description: IC DSPIC MCU/DSP 6K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F1010-30I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 6KB (2K x 24)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240002, DM300023, DM330011
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

38. Module: I
39. Module: I
40. Module: I
© 2010 Microchip Technology Inc.
The D_A Status bit (I2CxSTAT<5>) is set on a
slave data reception in the I2CxRCV register, but
is not set on a slave write to the I2CxTRN register.
In future silicon revisions, the D_A bit will be set on
a slave write to I2CxTRN.
Work around
Use the D_A Status bit for determining slave
reception status only. Do not use it for determining
slave transmission status.
Affected Silicon Revisions
The BCL bit in I2CSTAT can be cleared only with a
16-bit operation, and can be corrupted with 1-bit or
8-bit operations on I2CSTAT.
Work around
Use 16-bit operations to clear BCL.
Affected Silicon Revisions
If there are two I
them acts as the master receiver and the other
acts as the slave transmitter. If both devices are
configured for 10-bit Addressing mode, and have
the same value in the A10 and A9 bits of their
addresses: then, when the slave select address is
sent from the master, both the master and slave
acknowledge it. When the master sends out the
read operation, both the master and the slave
enter into Read mode, and both of them transmit
the data. The resultant data will be the ANDing of
the two transmissions.
Work around
In all I
A10 and A9, should be different.
Affected Silicon Revisions
A1
A1
A1
X
X
X
2
C devices, the addresses, as well as bits
A2
A2
A2
X
X
X
2
2
2
C
C
C
A3
A3
A3
X
X
X
2
C devices on the bus, one of
41. Module: I
42. Module: I
dsPIC30F1010/202X
In 10-bit Addressing mode, some address
matches do not set the RBF flag or load the
receive register, I2CxRCV, if the lower address
byte
particular, these include all addresses with the
form XX0000XXXX and XX1111XXXX, with the
following exceptions:
• 001111000X
• 011111001X
• 101111010X
• 111111011X
Work around
The lower address byte in 10-bit Addressing mode
should not be a reserved address.
Affected Silicon Revisions
If the I
with an address of 0x102, the I2CxRCV register
content for the lower address byte is 0x01, rather
than
acknowledges both address bytes.
Work around
None.
Affected Silicon Revisions
A1
A1
X
X
matches
2
C module is configured for a 10-bit slave
0x02.
A2
A2
X
X
2
2
C
C
A3
A3
X
X
However,
the
reserved
the
DS80445D-page 15
addresses.
I
2
C
module
In