PIC16F84A-20/P Microchip Technology, PIC16F84A-20/P Datasheet - Page 26

• Manufacturer Part Number: PIC16F84A-20/P
• Description: IC MCU FLASH 1KX14 EE 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F84A-20/P

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Eeprom Size: 64 x 8
• Ram Size: 68 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 68 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 1
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB16F84A - BOARD DAUGHTER ICEPIC3DVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F84A
6.3
The PIC16F84A differentiates between various kinds
of RESET:
• Power-on Reset (POR)
• MCLR during normal operation
• MCLR during SLEEP
• WDT Reset (during normal operation)
• WDT Wake-up (during SLEEP)
Figure 6-4 shows a simplified block diagram of the
On-Chip RESET Circuit. The MCLR Reset path has a
noise filter to ignore small pulses. The electrical speci-
fications state the pulse width requirements for the
MCLR pin.
FIGURE 6-4:
TABLE 6-3:
DS35007B-page 24
Power-on Reset
MCLR during normal operation
MCLR during SLEEP
WDT Reset (during normal operation)
WDT Wake-up
Interrupt wake-up from SLEEP
Legend: u = unchanged, x = unknown
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
MCLR
OSC1/
CLKIN
V
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
DD
RESET
2: See Table 6-5.
RC Osc
On-Chip
OST/PWRT
V
Module
Detect
DD
WDT
RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER
(1)
Rise
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
OST
PWRT
Reset
WDT
Time-out
External Reset
10-bit Ripple Counter
10-bit Ripple Counter
Power-on Reset
SLEEP
Condition
Enable PWRT
Enable OST
Some registers are not affected in any RESET condition;
their status is unknown on a POR and unchanged in any
other RESET. Most other registers are reset to a “RESET
state” on POR, MCLR or WDT Reset during normal oper-
ation and on MCLR during SLEEP. They are not affected
by a WDT Reset during SLEEP, since this RESET is
viewed as the resumption of normal operation.
Table 6-3 gives a description of RESET conditions for
the program counter (PC) and the STATUS register.
Table 6-4 gives a full description of RESET states for all
registers.
The TO and PD bits are set or cleared differently in dif-
ferent RESET situations (Section 6.7). These bits are
used in software to determine the nature of the RESET.
Program Counter
PC + 1
PC + 1
See Table 6-5
000h
000h
000h
000h
(1)
2001 Microchip Technology Inc.
S
R
STATUS Register
Q
0001 1xxx
000u uuuu
0001 0uuu
0000 1uuu
uuu0 0uuu
uuu1 0uuu
Chip_Reset