PIC16F737-I/SS Microchip Technology, PIC16F737-I/SS Datasheet - Page 264

• Manufacturer Part Number: PIC16F737-I/SS
• Description: IC PIC MCU FLASH 4KX14 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F737-I/SS

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC16F
• No. Of I/o's: 25
• Ram Memory Size: 368Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Interface: I2C, SPI, USART
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3DBF777 - BOARD DAUGHTER ICEPIC3AC164307 - MODULE SKT FOR PM3 28SSOPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PICmicro MID-RANGE MCU FAMILY
16.3.7
16.3.8
DS31016A-page 16-14
INTCON
PIR
PIE
SSPBUF
SSPCON
SSPSTAT
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'.
Note 1: The position of this bit is device dependent.
Name
2: These bits can also be named GPIE and GPIF.
Shaded cells are not used by the SSP in SPI mode.
Sleep Operation
Effects of a Reset
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
Bit 7
GIE
—
In master mode all module clocks are halted, and the transmission/reception will remain in that
state until the device wakes from sleep. After the device returns to normal mode, the module will
continue to transmit/receive data.
In slave mode, the SPI transmit/receive shift register operates asynchronously to the device. This
allows the device to be placed in sleep mode, and data to be shifted into the SPI transmit/receive
shift register. When all 8-bits have been received, the SSP interrupt flag bit will be set and if
enabled will wake the device from sleep.
A reset disables the SSP module and terminates the current transfer.
Table 16-1: Registers Associated with SPI Operation
SSPOV
PEIE
Bit 6
—
SSPEN
Bit 5
T0IE
D/A
INTE
Bit 4
CKP
P
SSPIF
SSPIE
SSPM3
RBIE
Bit 3
S
(1)
(1)
(2)
SSPM2
Bit 2
T0IF
R/W
SSPM1
Bit 1
INTF
UA
SSPM0
RBIF
Bit 0
BF
(2)
1997 Microchip Technology Inc.
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
--00 0000 --00 0000
Value on:
POR,
BOR
0
0
Value on
all other
resets
0
0