DSPIC30F3010-30I/SP Microchip Technology, DSPIC30F3010-30I/SP Datasheet - Page 6
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DSPIC30F3010-30I/SP
Manufacturer Part Number
DSPIC30F3010-30I/SP
Description
IC DSPIC MCU/DSP 24K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F3010-30ISO.pdf
(228 pages)
2.DSPIC30F3010-30ISO.pdf
(18 pages)
3.DSPIC30F3010-30ISO.pdf
(6 pages)
4.DSPIC30F3010-30ISO.pdf
(16 pages)
5.DSPIC30F3010-30ISO.pdf
(22 pages)
6.DSPIC30F3014-30IP.pdf
(244 pages)
Specifications of DSPIC30F3010-30I/SP
Program Memory Type
FLASH
Program Memory Size
24KB (8K x 24)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
20
Data Ram Size
1 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300027, DM330011, DM300018, DM183021
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F301030ISP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F3010-30I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F3010/3011
6. Module: Interrupt Controller – Sequential
EXAMPLE 5:
EXAMPLE 6:
EXAMPLE 7:
DS80216K-page 6
.include
...
DISI#2 ; protect the disable of INT1
BCLRIEC1, #INT1IE; disable interrupt 1
...
.include
...
__asm__ volatile (“DISI #0x1FFF”);
SRbits.IPL = 0x5;
DISICNT = 0x0;
#define DISI_PROTECT(X) {\
DISI_PROTECT(SRbits.IPL = 0x5);
When interrupt nesting is enabled (or NSTDIS
(INTCON1<15>) bit is ‘0’), the following sequence
of events will lead to an address error trap. The
generic terms “Interrupt 1” and “Interrupt 2” are
used to represent any two enabled dsPIC30F
interrupts.
1. Interrupt 1 processing begins.
2. Interrupt 1 is negated by user software by one
3. Interrupt 2 occurs with a priority higher than
__asm__ volatile (“DISI #0x1FFF”);\
X;
DISICNT = 0; }
of the following methods:
- CPU IPL is raised to Interrupt 1 IPL level or
- Interrupt 1 IPL is lowered to CPU IPL level or
- Interrupt 1 is disabled (Interrupt 1 IE bit set to
- Interrupt 1 flag is cleared
Interrupt 1.
higher or
lower or
‘0’) or
; next instruction protected by DISI
Interrupts
“p30fxxxx.inc”
“
USING DISI
RAISING CPU INTERRUPT PRIORITY LEVEL
USING MACRO
p30fxxxx.h
\
”
// safely modify the CPU IPL
// protect CPU IPL modification
// set CPU IPL to 5
// remove DISI protection
Work around
The user may disable interrupt nesting or execute
a DISI instruction before modifying the CPU IPL
or Interrupt 1 setting. A minimum DISI value of 2
is required if the DISI is executed immediately
before the CPU IPL or Interrupt 1 is modified, as
shown in Example 5. If the MPLAB C30 compiler
is being used, one must inspect the Disassembly
Listing in the MPLAB IDE file to determine the
exact number of cycles to disable level 1-6
interrupts. One may use a large DISI value and
then set the DISICNT register to zero, as shown in
Example 6. A macro may also be used to perform
this task, as shown in Example 7.
© 2008 Microchip Technology Inc.