DSPIC30F3014-30I/PT Microchip Technology, DSPIC30F3014-30I/PT Datasheet - Page 27

IC DSPIC MCU/DSP 24K 44TQFP

DSPIC30F3014-30I/PT

Manufacturer Part Number
DSPIC30F3014-30I/PT
Description
IC DSPIC MCU/DSP 24K 44TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F3014-30I/PT

Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
30
Flash Memory Size
24KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F301430IPT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F3014-30I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F3014-30I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
3.1.1
This architecture fetches 24-bit wide program memory.
Consequently,
However, as the architecture is modified Harvard, data
can also be present in program space.
There are two methods by which program space can
be accessed: via special table instructions, or through
the remapping of a 16K word program space page into
the upper half of data space (see
Access from Program Memory Using Program
Space
tions offer a direct method of reading or writing the lsw
of any address within program space, without going
through data space. The TBLRDH and TBLWTH instruc-
tions are the only method whereby the upper 8 bits of a
program space word can be accessed as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word-wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word, and TBLRDH and TBLWTH access the space
which contains the MS Data Byte.
Figure 3-3
ations and data space accesses (PSV = 1). Here,
P<23:0> refers to a program space word, whereas
D<15:0> refers to a data space word.
FIGURE 3-4:
 2010 Microchip Technology Inc.
Visibility”). The TBLRDL and TBLWTL instruc-
Program Memory
‘Phantom’ Byte
(read as ‘0’)
shows how the EA is created for table oper-
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
PC Address
0x000000
0x000002
0x000004
0x000006
instructions
PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD)
00000000
00000000
00000000
00000000
are
Section 3.1.2 “Data
always
23
aligned.
TBLRDL.W
16
A set of table instructions are provided to move byte or
word-sized data to and from program space. (See
Figure 3-4
1.
2.
3.
4.
dsPIC30F3014/4013
TBLRDL: Table Read Low
Word: Read the lsw of the program address;
P<15:0> maps to D<15:0>.
Byte: Read one of the LSBs of the program
address;
P<7:0> maps to the destination byte when byte
select = 0;
P<15:8> maps to the destination byte when byte
select = 1.
TBLWTL: Table Write Low (refer to
“Flash Program Memory”
programming)
TBLRDH: Table Read High
Word: Read the most significant word (msw) of
the program address; P<23:16> maps to D<7:0>;
D<15:8> will always be = 0.
Byte: Read one of the MSBs of the program
address;
P<23:16> maps to the destination byte when
byte select = 0;
The destination byte will always be = 0 when
byte select = 1.
TBLWTH: Table Write High (refer to
“Flash Program Memory”
Programming)
TBLRDL.B (Wn<0> = 1)
and
8
Figure
TBLRDL.B (Wn<0> = 0)
3-5.)
for details on Flash
for details on Flash
0
DS70138G-page 27
Section 5.0
Section 5.0

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