PIC16LC923-04/L Microchip Technology, PIC16LC923-04/L Datasheet - Page 17
![IC MCU OTP 4KX14 LCD DVR 68PLCC](/photos/12/13/121323/c04-049_l_sml.jpg)
PIC16LC923-04/L
Manufacturer Part Number
PIC16LC923-04/L
Description
IC MCU OTP 4KX14 LCD DVR 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheet
1.PIC16C923-04L.pdf
(189 pages)
Specifications of PIC16LC923-04/L
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
176 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
Processor Series
PIC16LC
Core
PIC
Data Bus Width
8 bit
Data Ram Size
176 B
Interface Type
I2C, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
25
Number Of Timers
3
Operating Supply Voltage
2.5 V to 6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LC923-04/L
Manufacturer:
Microchip Technology
Quantity:
1 964
Company:
Part Number:
PIC16LC923-04/L
Manufacturer:
Microchip Technology
Quantity:
10 000
4.0
4.1
The PIC16C9XX family has a 13-bit program counter
capable of addressing an 8K x 14 program memory
space.
Only the first 4K x 14 (0000h-0FFFh) is physically
implemented. Accessing a location above the physi-
cally implemented addresses will cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 4-1: PROGRAM MEMORY MAP
1997 Microchip Technology Inc.
CALL, RETURN
RETFIE, RETLW
MEMORY ORGANIZATION
Program Memory Organization
Memory (Page 0)
Memory (Page 1)
On-chip Program
On-chip Program
AND STACK
Interrupt Vector
Stack Level 1
Stack Level 8
Reset Vector
PC<12:0>
13
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
1FFFh
4.2
The data memory is partitioned into four Banks which
contain the General Purpose Registers and the Special
Function Registers. Bits RP1 and RP0 are the bank
select bits.
RP1:RP0 (STATUS<6:5>)
11 = Bank 3 (180h-1FFh)
10 = Bank 2 (100h-17Fh)
01 = Bank 1 (80h-FFh)
00 = Bank 0 (00h-7Fh)
The lower locations of each Bank are reserved for the
Special Function Registers. Above the Special Func-
tion Registers are General Purpose Registers imple-
mented as static RAM. All four banks contain special
function registers. Some “high use” special function
registers are mirrored in other banks for code reduction
and quicker access.
4.2.1
The register file can be accessed either directly, or indi-
rectly
(Section 4.5).
The following General Purpose Registers are not phys-
ically implemented:
• F0h-FFh of Bank 1
• 170h-17Fh of Bank 2
• 1F0h-1FFh of Bank 3
These locations are used for common access across
banks.
through
Data Memory Organization
GENERAL PURPOSE REGISTER FILE
the
File
PIC16C9XX
Select
DS30444E - page 17
Register
FSR