PIC24HJ64GP502-I/SO Microchip Technology, PIC24HJ64GP502-I/SO Datasheet - Page 39
![IC PIC MCU FLASH 64K 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC24HJ64GP502-I/SO
Manufacturer Part Number
PIC24HJ64GP502-I/SO
Description
IC PIC MCU FLASH 64K 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP302-ISO.pdf
(368 pages)
3.PIC24HJ32GP302-ISO.pdf
(8 pages)
4.PIC24HJ32GP302-ISO.pdf
(12 pages)
5.PIC24HJ32GP304-EML.pdf
(356 pages)
Specifications of PIC24HJ64GP502-I/SO
Program Memory Type
FLASH
Program Memory Size
64KB (22K x 24)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM300027
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel / 12 bit, 10 Channel
Controller Family/series
PIC24
No. Of I/o's
21
Ram Memory Size
4KB
Cpu Speed
40MIPS
No. Of Timers
7
Embedded Interface Type
CAN, I2C, SPI, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164339 - MODULE SKT FOR PM3 28SOIC
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24HJ64GP502-I/SO
Manufacturer:
MICROCHIP
Quantity:
12 000
TABLE 5-5:
© 2010 Microchip Technology Inc.
Step 1: Exit the Reset vector.
Step 2: Set the NVMCON to program 64 instruction words.
Step 3: Initialize the write pointer (W7) for TBLWT instruction.
Step 4: Initialize the read pointer (W6) and load W0:W5 with the next 4 instruction words to program.
Step 5: Set the read pointer (W6) and load the (next set of) write latches.
Step 6: Repeat steps 4-5 sixteen times to load the write latches for 64 instructions.
Step 7: Initiate the write cycle.
Command
(Binary)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY
040200
040200
000000
24001A
883B0A
200xx0
880190
2xxxx7
2xxxx0
2xxxx1
2xxxx2
2xxxx3
2xxxx4
2xxxx5
EB0300
000000
BB0BB6
000000
000000
BBDBB6
000000
000000
BBEBB6
000000
000000
BB1BB6
000000
000000
BB0BB6
000000
000000
BBDBB6
000000
000000
BBEBB6
000000
000000
BB1BB6
000000
000000
A8E761
000000
000000
000000
000000
(Hex)
Data
GOTO
GOTO
NOP
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
CLR W6
NOP
TBLWTL[W6++], [W7]
NOP
NOP
TBLWTH.B[W6++], [W7++]
NOP
NOP
TBLWTH.B[W6++], [++W7]
NOP
NOP
TBLWTL[W6++], [W7++]
NOP
NOP
TBLWTL[W6++], [W7]
NOP
NOP
TBLWTH.B[W6++], [W7++]
NOP
NOP
TBLWTH.B[W6++], [++W7]
NOP
NOP
TBLWTL[W6++], [W7++]
NOP
NOP
BSET
NOP
NOP
NOP
NOP
0x200
0x200
#0x4001, W10
W10, NVMCON
#<DestinationAddress23:16>, W0
W0, TBLPAG
#<DestinationAddress15:0>, W7
#<LSW0>, W0
#<MSB1:MSB0>, W1
#<LSW1>, W2
#<LSW2>, W3
#<MSB3:MSB2>, W4
#<LSW3>, W5
NVMCON, #WR
Description
DS70152H-page 39