PIC16F76-I/ML Microchip Technology, PIC16F76-I/ML Datasheet - Page 264
PIC16F76-I/ML
Manufacturer Part Number
PIC16F76-I/ML
Description
IC MCU FLASH 8KX14 A/D 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F73-ISP.pdf
(174 pages)
5.PIC16F73-ISP.pdf
(14 pages)
6.PIC16F73-ISP.pdf
(12 pages)
Specifications of PIC16F76-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
22
Number Of Timers
3 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
For Use With
XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC16F76-I/MLR
PIC16F76-I/MLR
PIC16F76I/ML
PIC16F76-I/MLR
PIC16F76I/ML
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F73-ISP PDF datasheet #4
- PIC16F73-ISP PDF datasheet #5
- PIC16F73-ISP PDF datasheet #6
- Current page: 264 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
16.3.7
16.3.8
DS31016A-page 16-14
INTCON
PIR
PIE
SSPBUF
SSPCON
SSPSTAT
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'.
Note 1: The position of this bit is device dependent.
Name
2: These bits can also be named GPIE and GPIF.
Shaded cells are not used by the SSP in SPI mode.
Sleep Operation
Effects of a Reset
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
Bit 7
GIE
—
In master mode all module clocks are halted, and the transmission/reception will remain in that
state until the device wakes from sleep. After the device returns to normal mode, the module will
continue to transmit/receive data.
In slave mode, the SPI transmit/receive shift register operates asynchronously to the device. This
allows the device to be placed in sleep mode, and data to be shifted into the SPI transmit/receive
shift register. When all 8-bits have been received, the SSP interrupt flag bit will be set and if
enabled will wake the device from sleep.
A reset disables the SSP module and terminates the current transfer.
Table 16-1: Registers Associated with SPI Operation
SSPOV
PEIE
Bit 6
—
SSPEN
Bit 5
T0IE
D/A
INTE
Bit 4
CKP
P
SSPIF
SSPIE
SSPM3
RBIE
Bit 3
S
(1)
(1)
(2)
SSPM2
Bit 2
T0IF
R/W
SSPM1
Bit 1
INTF
UA
SSPM0
RBIF
Bit 0
BF
(2)
1997 Microchip Technology Inc.
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
--00 0000 --00 0000
Value on:
POR,
BOR
0
0
Value on
all other
resets
0
0
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