PIC24HJ64GP206-I/PT Microchip Technology, PIC24HJ64GP206-I/PT Datasheet - Page 10
![IC PIC MCU FLASH 32KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC24HJ64GP206-I/PT
Manufacturer Part Number
PIC24HJ64GP206-I/PT
Description
IC PIC MCU FLASH 32KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ64GP206-IPT.pdf
(292 pages)
3.PIC24HJ64GP206-IPT.pdf
(8 pages)
4.PIC24HJ64GP206-IPT.pdf
(20 pages)
5.PIC24HJ64GP206-IPT.pdf
(26 pages)
6.PIC24HJ128GP206-IPT.pdf
(286 pages)
7.PIC24HJ128GP306-IPT.pdf
(288 pages)
Specifications of PIC24HJ64GP206-I/PT
Program Memory Type
FLASH
Program Memory Size
64KB (22K x 24)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 18x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN, I2C, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
13
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 18 Channel
Controller Family/series
PIC24
No. Of I/o's
53
Ram Memory Size
8KB
Cpu Speed
40MIPS
No. Of Timers
13
Embedded Interface Type
I2C, SPI, UART
Rohs Compliant
Yes
Height
1 mm
Length
10 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
PIC24HJ64GP206-I/PT
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Microchi
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297
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Quantity:
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Quantity:
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Quantity:
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Part Number:
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Manufacturer:
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Quantity:
20 000
PIC24HJXXXGPX06/X08/X10
6. Module: Output Compare
7. Module: SPI
DS80444D-page 10
The output compare module will miss a compare
event when the current duty cycle register
(OCxRS) value is 0x0000 (0% duty cycle) and the
OCxRS register is updated with a value of 0x0001.
The compare event is only missed the first time a
value of 0x0001 is written to OCxRS and the PWM
output remains low for one PWM period.
Subsequent PWM high and low times occur as
expected.
Work around
None. If the current OCxRS register value is
0x0000, avoid writing a value of 0x0001 to
OCxRS. Instead, write a value of 0x0002;
however, in this case the duty cycle will be slightly
different from the desired value.
Affected Silicon Revisions
The SPI module will fail to generate frame
synchronization pulses when configured in the
Frame Master mode if the start of data is selected
to
synchronization pulse (FRMEN = 1, SPIFSD = 0,
FRMDLY = 1). Synchronization pulses also will not
be generated if FRMDLY = 0 and SMP = 0.
However, the module functions correctly in Frame
Slave mode, and also when FRMDLY = 0 and
SMP = 1.
Work around
If DMA is not being used, manually drive the SSx
pin (x = 1 or 2) high using the associated PORT
register, and then drive it low after the required
1 bit-time pulse width. This operation needs to be
performed when the transmit buffer is written.
If DMA is being used, and if no other peripheral
modules are using DMA transfers, use a Timer
interrupt to periodically generate the frame
synchronization
described above) after every 8- or 16-bit period
(depending on the data word size, which is
configured using the MODE 16-bit).
Affected Silicon Revisions
A2
A2
X
X
coincide
A3
A3
X
X
A4
A4
X
X
with
pulse
the
(using
start
of
the
the
method
frame
8. Module: SPI
The SPI module slave select functionality (enabled
by setting SSEN = 1) will not function correctly.
Whether the SSx pin (x = 1 or 2) is high or low, the
SPI data transfer will be completed and an
interrupt will be generated.
Work around
If DMA is not being used, poll the SSx pin state
using the Change Notification (CN) pin associated
to the SSx pin as follows:
1. Disable the SPIx module by clearing the
2. Clear the SSEN bit in the SPIxCON1 register
3. Ensure that the CNx pin is configured as a
4. Enable interrupts for the selected CNx pin by
5. Turn on the weak pull-up device for the
6. Clear the CNIF interrupt flag in the IFSx
7. Select the desired interrupt priority for CNx
8. Enable CNx interrupts using the CNIE control
9. In the CNx Interrupt Service Routine, read the
If DMA is being used, no work around exists.
Affected Silicon Revisions
A2
X
SPIEN bit in the SPIxSTAT register.
to allow the I/O port to control the SSx pin.
digital input by setting the associated bit in the
TRISx register.
setting the appropriate bits in the CNEN1 and
CNEN2 registers.
selected CNx pins by setting the appropriate
bits in the CNPU1 and CNPU2 registers.
register.
interrupts using the CNIP<2:0> control bits in
the IPCx register.
bit in the IECx register.
PORTx register associated to the SSx pin:
a) if the PORTx bit is ‘0’ – enable the SPIx
b) if the PORTx bit is ‘1’ – disable the SPIx
module by setting the SPIEN bit, and
perform the required data read/write.
module by setting the SPIEN bit, clear the
SPI interrupt flag (SPIxIF), perform a
dummy read of the SPIxBUF register,
and return from the Interrupt Service
Routine (ISR).
A3
X
A4
X
© 2010 Microchip Technology Inc.