DSPIC33FJ16GS504-I/PT Microchip Technology, DSPIC33FJ16GS504-I/PT Datasheet - Page 3

• Manufacturer Part Number: DSPIC33FJ16GS504-I/PT
• Description: IC DSPIC MCU/DSP 16K 44-TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16GS504-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 2:
© 2010 Microchip Technology Inc.
Note 1:
Programming
Auxiliary PLL
Comparator
Comparator
High Speed
Operations
Reserved
PGEC3/
Module
PGED3
Analog
UART
UART
UART
PWM
PWM
PWM
PWM
ADC
PSV
Pins
I
I
2
2
C
C
Only those issues indicated in the last column apply to the current silicon revision.
IrDA
SILICON ISSUE SUMMARY (CONTINUED)
8-bit Operating
in Sleep Mode
Current Reset
Programming
UxE Interrupt
Consumption
PWM Module
Current Limit
Decoder and
Independent
Sleep Mode
Addressing
Addressing
Addressing
Generation
Time Base
Frequency
Reference
Character
Bandgap
Feature
Internal
Voltage
Current
Enable
Device
Modes
®
Break
Mode
Mode
10-bit
Mode
10-bit
Mode
Input
Encoder/
—
Number
Item
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
When using the PGEC3/PGED3 pins for device
programming, the programming time may be slower as
compared to other available PGECx/PGEDx pin pairs.
The UART module will not generate back-to-back break
characters.
Cycle-by-cycle current limit operation does not work when
the PWM module is configured for Center-Aligned mode.
Current Reset mode does not work when the current limit
source (CLSRC) occurs during and persists past the
assertive time interval of the PWM, and leading-edge
blanking time is less than the PWM assertive time interval.
When the UART module is operating in 8-bit mode
(PDSEL = 0x) and using the IrDA encoder/decoder
(IREN = 1), the module incorrectly transmits a data
payload of 80h as 00h.
The UART error interrupt may not occur, or may occur at
an incorrect time, if multiple errors occur during a short
period of time.
When the I
an address of 0x102, the I2CxRCV register content for the
lower address byte is 0x01 rather than 0x02.
The 10-bit slave does not set the RBF flag or load the
I2CxRCV register, on address match if the Least
Significant bits (LSbs) of the address are the same as the
7-bit reserved addresses.
An address error trap occurs in certain addressing modes
when accessing the first four bytes of any PSV page.
The Comparator fails to wake the CPU from Sleep mode
when the internal voltage reference is used.
When updating the frequency on the fly, Push-Pull PWM
outputs may not be synchronized with other PWM output
modes.
The Internal Bandgap Reference Voltage (INTREF) for the
Analog Comparator does not meet the stated accuracy
specifications.
For extended temperature devices, the Auxiliary PLL input
frequency does not meet the published specification
range.
If the ADC module is in an enabled state when the device
enters Sleep Mode, the power-down current (I
device may exceed the device data sheet specifications.
A glitch may be observed on the PWM pins when the
PWM module is enabled after assignment of pin
ownership to the PWM module.
2
C module is configured as a 10-bit slave with
Issue Summary
—
PD
) of the
DS80439H-page 3
A2
Revisions
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Affected
A3
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A4
(1)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X