PIC24HJ128GP202-I/SO Microchip Technology, PIC24HJ128GP202-I/SO Datasheet - Page 29
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PIC24HJ128GP202-I/SO
Manufacturer Part Number
PIC24HJ128GP202-I/SO
Description
IC PIC MCU FLASH 128K 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP302-ISO.pdf
(368 pages)
3.PIC24HJ32GP302-ISO.pdf
(8 pages)
4.PIC24HJ32GP302-ISO.pdf
(12 pages)
5.PIC24HJ32GP304-EML.pdf
(356 pages)
Specifications of PIC24HJ128GP202-I/SO
Program Memory Type
FLASH
Program Memory Size
128KB (43K x 24)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM300027
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 12-bit
Controller Family/series
PIC24
No. Of I/o's
21
Ram Memory Size
8KB
Cpu Speed
40MIPS
No. Of Timers
7
Embedded Interface Type
I2C, SPI, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164339 - MODULE SKT FOR PM3 28SOIC
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
4.2.12
The QBLANK command queries the programming
executive to determine if the contents of code memory
are blank (contains all ‘1’s). The size of code memory
to check must be specified in the command.
The Blank Check for code memory begins at [Addr] and
advances toward larger addresses for the specified
number of instruction words.
QBLANK returns a QE_Code of 0xF0 if the specified
code memory is blank; otherwise, QBLANK returns a
QE_Code of 0x0F.
Expected Response (2 words for blank device):
0x1EF0
0x0002
Expected Response (2 words for non-blank device):
0x1E0F
0x0002
© 2010 Microchip Technology Inc.
15
Opcode
Length
Size
Addr_MSB
Addr_LSW
Note:
Opcode
Field
Reserved
Reserved
12 11
QBLANK COMMAND
The QBLANK command does not check
the system operation Configuration bits
since these bits are not set to ‘1’ when a
Chip Erase is performed.
0xE
0x5
Length of program memory to check
(in 24-bit words) + Addr_MS
Most Significant Byte of the 24-bit
address
Least Significant 16 bits of the 24-bit
address
Addr_LSW
Size_LSW
Description
Length
Addr_MSB
Size_MSB
0
4.2.13
The QVER command queries the version of the
programming executive software stored in test
memory. The “version.revision” information is returned
in the response’s QE_Code using a single byte with the
following format: main version in upper nibble and
revision in the lower nibble (i.e., 0x23 means
version 2.3 of programming executive software).
Expected Response (2 words):
0x1BMN (where “MN” stands for version M.N)
0x0002
4.3
The programming executive sends a response to the
programmer for each command that it receives. The
response indicates if the command was processed
correctly. It includes any required response data or
error data.
The programming executive response set is shown in
Table
and description for each response. The response format
is described in
TABLE 4-2:
15
Opcode
Length
0x1
0x2
0x3
Opcode
Opcode
Field
4-2. This table contains the opcode, mnemonic
Programming Executive
Responses
12 11
QVER COMMAND
PASS
FAIL
NACK
Mnemonic
Section 4.3.1 “Response
0xB
0x1
PROGRAMMING EXECUTIVE
RESPONSE OPCODES
Command successfully
processed.
Command unsuccessfully
processed.
Command not known.
Description
Length
Description
DS70152H-page 29
Format”.
0