DSPIC33FJ64MC202-I/SP Microchip Technology, DSPIC33FJ64MC202-I/SP Datasheet - Page 241
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DSPIC33FJ64MC202-I/SP
Manufacturer Part Number
DSPIC33FJ64MC202-I/SP
Description
IC DSPIC MCU/DSP 64K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
2.DSPIC33FJ32MC302-ISO.pdf
(436 pages)
3.DSPIC33FJ64MC202-ESO.pdf
(424 pages)
Specifications of DSPIC33FJ64MC202-I/SP
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Data Ram Size
8 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- DSPIC33FJ32MC202-IMM PDF datasheet
- DSPIC33FJ32MC302-ISO PDF datasheet #2
- DSPIC33FJ64MC202-ESO PDF datasheet #3
- Current page: 241 of 436
- Download datasheet (6Mb)
20.0
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules
available
dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/
X04 device family. The UART is a full-duplex
asynchronous system that can communicate with
peripheral devices, such as personal computers,
LIN 2.0, RS-232 and RS-485 interfaces. The module
also supports a hardware flow control option with the
UxCTS and UxRTS pins and also includes an IrDA
encoder and decoder.
FIGURE 20-1:
© 2011 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
Note 1: This data sheet summarizes the features
Note 1: Both UART1 and UART2 can trigger a DMA data transfer.
2: Some registers and associated bits
2: If DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
of
dsPIC33FJ64MCX02/X04
dsPIC33FJ128MCX02/X04
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Section 17. UART”
(DS70188) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
(i.e., UTXISEL<1:0> = 00 and URXISEL<1:0> = 00).
in
the
the
UART SIMPLIFIED BLOCK DIAGRAM
dsPIC33FJ32MC302/304,
dsPIC33FJ32MC302/304,
Hardware Flow Control
Baud Rate Generator
UART Transmitter
UART Receiver
IrDA
family
®
and
of
in
®
The primary features of the UART module are:
• Full-Duplex, 8- or 9-bit Data Transmission through
• Even, Odd or No Parity Options (for 8-bit data)
• One or two stop bits
• Hardware flow control option with UxCTS and
• Fully integrated Baud Rate Generator with 16-bit
• Baud rates ranging from 10 Mbps to 38 bps at 40
• Baud rates ranging from 4 Mbps to 61 bps at 4x mode
• 4-deep First-In First-Out (FIFO) Transmit Data
• 4-deep FIFO Receive Data buffer
• Parity, framing and buffer overrun error detection
• Support for 9-bit mode with Address Detect
• Transmit and Receive interrupts
• A separate interrupt for all UART error conditions
• Loopback mode for diagnostic support
• Support for sync and break characters
• Support for automatic baud rate detection
• IrDA
• 16x baud clock output for IrDA
A simplified block diagram of the UART module is
shown in
these key hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
the UxTX and UxRX pins
UxRTS pins
prescaler
MIPS
at 40 MIPS
buffer
(9th bit = 1)
®
encoder and decoder logic
Figure
20-1. The UART module consists of
BCLK
UxRTS
UxCTS
UxRX
UxTX
®
support
DS70291E-page 241
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