DSPIC33FJ16GS504-I/ML Microchip Technology, DSPIC33FJ16GS504-I/ML Datasheet - Page 337

• Manufacturer Part Number: DSPIC33FJ16GS504-I/ML
• Description: IC DSPIC MCU/DSP 16K 44-QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16GS504-I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Core Frequency: 40MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 35
• Flash Memory Size: 16KB
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE A-2:
© 2009 Microchip Technology Inc.
Section 24.0 “Electrical
Characteristics”
Section Name
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
MAJOR SECTION UPDATES (CONTINUED)
Updated Typical values for Thermal Packaging Characteristics (see
Table 24-3).
Updated Min and Max values for parameter DC12 (RAM Data Retention
Voltage) and added Note 4 (see Table 24-4).
Updated Characteristics for I/O Pin Input Specifications (see Table 24-9).
Added I
Updated Program Memory values for parameters 136, 137, and 138
(renamed to 136a, 137a, and 138a), added parameters 136b, 137b, and
138b, and added Note 2 (see Table 24-12).
Added parameter OS42 (G
(see Table 24-16).
Updated Conditions for symbol T
(PWM Input Clock) to the High-Speed PWM Module Timing Requirements
(see Table 24-29).
Updated parameters AD01 and AD02 in the 10-bit High-Speed A/D Module
Specifications (see Table 24-36).
Updated parameters AD50b, AD55b, and AD56b, and removed parameters
AD57b and AD60b from the 10-bit High-Speed A/D Module Timing
Requirements (see Table 24-37).
SOURCE
Preliminary
to I/O Pin Output Specifications (see Table 24-10).
M
Update Description
) to the External Clock Timing Requirements
PDLY
(Tap Delay) and added symbol A
DS70318D-page 335
CLK