PIC16LF873A-I/SS Microchip Technology, PIC16LF873A-I/SS Datasheet - Page 117

• Manufacturer Part Number: PIC16LF873A-I/SS
• Description: IC MCU FLASH 4KX14 EE A/D 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF873A-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 28-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Eeprom Size: 128 x 8
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Data Rom Size: 128 B
• Height: 1.75 mm
• Length: 10.2 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 5.3 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC16LF873AI/SS

10.2
In this mode, the USART uses standard Non-Return-
to-Zero (NRZ) format (one Start bit, eight or nine data
bits and one Stop bit). The most common data format
is 8 bits. An on-chip, dedicated, 8-bit Baud Rate
Generator can be used to derive standard baud rate
frequencies from the oscillator. The USART transmits
and receives the LSb first. The transmitter and receiver
are functionally independent but use the same data
format and baud rate. The baud rate generator
produces a clock, either x16 or x64 of the bit shift rate,
depending on bit BRGH (TXSTA<2>). Parity is not
supported by the hardware but can be implemented in
software (and stored as the ninth data bit).
Asynchronous mode is stopped during Sleep.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the
following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
10.2.1
The USART transmitter block diagram is shown in
Figure 10-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer, TXREG.
The TXREG register is loaded with data in software.
The TSR register is not loaded until the Stop bit has
been transmitted from the previous load. As soon as
the Stop bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one T
flag bit, TXIF (PIR1<4>), is set. This interrupt can be
FIGURE 10-1:
 2003 Microchip Technology Inc.
USART Asynchronous Mode
USART ASYNCHRONOUS
TRANSMITTER
TXIE
Interrupt
CY
), the TXREG register is empty and
TXIF
TXEN
Baud Rate Generator
USART TRANSMIT BLOCK DIAGRAM
SPBRG
Baud Rate CLK
MSb
(8)
TX9D
TXREG Register
TSR Register
TX9
8
Data Bus
enabled/disabled by setting/clearing enable bit, TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit, TRMT (TXSTA<1>),
shows the status of the TSR register. Status bit TRMT
is a read-only bit which is set when the TSR register is
empty. No interrupt logic is tied to this bit so the user
has to poll this bit in order to determine if the TSR
register is empty.
Transmission is enabled by setting enable bit, TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the Baud Rate Generator (BRG) has produced a
shift clock (Figure 10-2). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally, when transmission
is first started, the TSR register is empty. At that point,
transfer to the TXREG register will result in an immedi-
ate transfer to TSR, resulting in an empty TXREG. A
back-to-back transfer is thus possible (Figure 10-3).
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. As a result, the RC6/TX/CK pin will revert
to high-impedance.
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG reg-
ister. This is because a data write to the TXREG regis-
ter can result in an immediate transfer of the data to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit may be loaded in the TSR
register.
Note 1: The TSR register is not mapped in data
LSb
0
2: Flag bit TXIF is set when enable bit TXEN
TRMT
memory so it is not available to the user.
is set. TXIF is cleared by loading TXREG.
and Control
Pin Buffer
SPEN
PIC16F87XA
RC6/TX/CK pin
DS39582B-page 115