DSPIC33FJ128GP206-I/PT Microchip Technology, DSPIC33FJ128GP206-I/PT Datasheet - Page 17
![IC DSPIC MCU/DSP 128K 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
DSPIC33FJ128GP206-I/PT
Manufacturer Part Number
DSPIC33FJ128GP206-I/PT
Description
IC DSPIC MCU/DSP 128K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12GP201-ISO.pdf
(90 pages)
2.DSPIC33FJ64GP206-IPT.pdf
(322 pages)
3.DSPIC33FJ64GP206-IPT.pdf
(28 pages)
4.DSPIC33FJ128MC506-IPT.pdf
(24 pages)
Specifications of DSPIC33FJ128GP206-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
64-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
53
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 18x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Data Ram Size
8 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128GP206-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
33. Module: DMA
34. Module: DMA
© 2010 Microchip Technology Inc.
When a DMA channel is enabled in Single-Shot
mode while the device is in Idle mode, and the
corresponding peripheral is active and configured
to operate during Idle mode, the DMA channel
may not become disabled immediately upon
transferring the required amount of data.
As a result, the number of bytes or words of data
transferred may exceed the DMA transfer count
specified in the DMAxCNT register.
For example, if DMA transfers are active for both
SPI byte transmissions and receptions, and only
the receive DMA channel interrupt is enabled for
waking up the device from Idle mode, an extra byte
will be transmitted by the time the device wakes up
from Idle mode.
Work around
None.
Affected Silicon Revisions
A DMA error trap may not be generated when the
device is in Doze mode.
Work around
None.
Affected Silicon Revisions
A2
A2
X
X
A3
A3
X
X
A4
A4
X
X
35. Module: Output Compare
36. Module: UART
37. Module: UART
When the output compare module is operated in
the Dual Compare Match mode, a timer compare
match with the value in the OCxR register sets the
OCx output, producing a rising edge on the OCx
pin. Then, when a timer compare match with the
value in the OCxRS register occurs, the OCx
output is reset, producing a falling edge on the
OCx pin.
The above statement applies to all conditions
except when the difference between OCxR and
OCxRS is 1. In this case, the output compare
module may miss the Reset compare event, and
cause the OCx pin to remain continuously high.
This condition will remain until the difference
between values in the OCxR and OCxRS registers
is made greater than 1.
Work around
Ensure in software that the difference between
values in OCxR and OCxRS registers is
maintained greater than 1.
Affected Silicon Revisions
When the UART is in 4x mode (BRGH = 1) and
using two Stop bits (STSEL = 1), it may sample the
first Stop bit instead of the second one.
This issue does not affect the other UART
configurations.
Work around
Use the 16x baud rate option (BRGH = 0) and
adjust the baud rate accordingly.
Affected Silicon Revisions
When an auto-baud is detected, the receive
interrupt may occur twice. The first interrupt occurs
at the beginning of the Start bit and the second
after reception of the Sync field character.
Work around
If an extra interrupt is detected, ignore the
additional interrupt.
Affected Silicon Revisions
A2
A2
A2
X
X
X
A3
A3
A3
X
X
X
A4
A4
A4
X
X
X
DS80446D-page 17