PIC16LF876A-I/SP Microchip Technology, PIC16LF876A-I/SP Datasheet - Page 93
![IC MCU FLASH 8KX14 EE A/D 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC16LF876A-I/SP
Manufacturer Part Number
PIC16LF876A-I/SP
Description
IC MCU FLASH 8KX14 EE A/D 28DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF876A-I/SP
Program Memory Type
FLASH
Program Memory Size
14KB (8K x 14)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
I2C/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
22
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
Minimum Operating Temperature
- 40 C
On-chip Adc
5-ch x 10-bit
Package
28SPDIP
Device Core
PIC
Family Name
PIC16
Maximum Speed
20 MHz
Data Rom Size
256 B
Height
3.3 mm
Length
34.67 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
7.24 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
PIC16LF876AI/SP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16LF876A-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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9.4.4.5
When the CKP bit is cleared, the SCL output is forced
to ‘0’; however, setting the CKP bit will not assert the
SCL output low until the SCL output is already sampled
low. Therefore, the CKP bit will not assert the SCL line
until an external I
asserted the SCL line. The SCL output will remain low
until the CKP bit is set and all other devices on the I
bus have deasserted SCL. This ensures that a write to
the CKP bit will not violate the minimum high time
requirement for SCL (see Figure 9-12).
FIGURE 9-12:
2003 Microchip Technology Inc.
SDA
SCL
CKP
WR
SSPCON
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Clock Synchronization and the
CKP Bit
2
C master device has already
CLOCK SYNCHRONIZATION TIMING
DX
Master device
asserts clock
2
C
Master device
deasserts clock
PIC16F87XA
DS39582B-page 91
DX-1
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