DSPIC30F4012-30I/SO Microchip Technology, DSPIC30F4012-30I/SO Datasheet - Page 62

• Manufacturer Part Number: DSPIC30F4012-30I/SO
• Description: IC DSPIC MCU/DSP 48K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4012-30I/SO

• Program Memory Type: FLASH
• Program Memory Size: 48KB (16K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 20
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300027, DM330011, DM300018, DM183021
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F401230ISO

dsPIC30F4011/4012
FIGURE 8-2:
8.2
The use of the ADPCFG and TRIS registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bit set (input). If the TRIS bit is cleared
(output), the digital output level (V
converted.
When reading the PORT register, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an ana-
log input. Analog levels on any pin that is defined as a
digital input (including the ANx pins), may cause the
input buffer to consume current that exceeds the
device specifications.
DS70135G-page 62
Configuring Analog Port Pins
Data Bus
WR TRIS
WR LAT +
WR PORT
BLOCK DIAGRAM OF A SHARED PORT STRUCTURE
Read PORT
Peripheral Output Enable
Peripheral Output Data
Peripheral Input Data
Peripheral Module Enable
Peripheral Module
PIO Module
Read TRIS
Read LAT
OH
TRIS Latch
Data Latch
D
D
CK
CK
or V
OL
Q
Q
) will be
8.2.1
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be a NOP.
EXAMPLE 8-1:
MOV
MOV
NOP
BTSS PORTB, #13 ; Next Instruction
1
0
1
0
0xFF00, W0 ; Configure PORTB<15:8>
W0, TRISBB ; and PORTB<7:0> as outputs
Output Data
Output Enable
I/O PORT WRITE/READ TIMING
Output Multiplexers
Input Data
; as inputs
; Delay 1 cycle
I/O Cell
PORT WRITE/READ
EXAMPLE
© 2010 Microchip Technology Inc.
I/O Pad