PIC18LF2523-I/SO Microchip Technology, PIC18LF2523-I/SO Datasheet - Page 2
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PIC18LF2523-I/SO
Manufacturer Part Number
PIC18LF2523-I/SO
Description
IC PIC MCU FLASH 16KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2423-ISP.pdf
(54 pages)
3.PIC18F2423-ISP.pdf
(8 pages)
4.PIC18F2423-ISP.pdf
(34 pages)
5.PIC18F2523-ISO.pdf
(392 pages)
Specifications of PIC18LF2523-I/SO
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
1.5KB
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM163022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 10 Channel
A/d Bit Size
12 bit
A/d Channels Available
10
Height
2.31 mm
Length
17.9 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
7.5 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
PIC18F2423/2523/4423/4523
2. Module: MSSP
3. Module: Timer1 and Timer3
EXAMPLE 1:
DS80289E-page 2
CLRF
MOVLW
MOVWF
With MSSP in SPI Master mode, F
Timer2/2 clock rate, and CKE = 0, a write collision
may occur if SSPBUF is loaded immediately after
the transfer is complete. A delay may be required
after the MSSP Interrupt Flag bit, SSPIF, is set or
the Buffer Full bit, BF, is set and before writing
SSPBUF. If the delay is insufficiently short, a write
collision may occur, as indicated by the WCOL bit
being set.
Work around
Add a software delay of one SCK period after
detecting the completed transfer and prior to
updating the SSPBUF contents. Verify the WCOL
bit is clear after writing SSPBUF. If the WCOL is
set, clear the bit in software and rewrite the
SSPBUF register.
Date Codes that pertain to this issue:
All engineering and production devices.
For Timer1 or Timer3, if the TMRxH and TMRxL
registers are written to in consecutive instruction
cycles, the timer may not be updated with the
correct value when configured for externally
clocked 8-Bit Asynchronous mode (T1CON<7:0>
or T3CON<7:0> = 0xxx x111).
Work around
Insert a delay of one or more instruction cycles
between writes to TMRxH and TMRxL. This delay
can be a NOP, or any instruction that does not
access the Timer registers (Example 1).
Date Codes that pertain to this issue:
All engineering and production devices.
TMR1H
T1Offset
TMR1L
; 1 Tcy delay
OSC
/64 or
4. Module: ECCP (PWM Mode)
Note:
When configured for half-bridge operation with
dead band (CCPxCON<7:6> = 10), the PWM out-
put may be corrupted for certain values of the
PWM duty cycle. This occurs when these
additional criteria are also met:
• a non-zero, dead-band delay is specified
• the duty cycle has a value of 0 through 3, or
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
(PDC6:PDC0 > 0); and
4n + 3 (n ≥ 1).
The ECCP module is implemented only in
40/44-pin devices.
© 2007 Microchip Technology Inc.