PIC24FJ128GB106-I/PT Microchip Technology, PIC24FJ128GB106-I/PT Datasheet - Page 7
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PIC24FJ128GB106-I/PT
Manufacturer Part Number
PIC24FJ128GB106-I/PT
Description
IC PIC MCU FLASH 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ128GA106-IPT.pdf
(52 pages)
2.PIC24FJ64GB106-IPT.pdf
(16 pages)
3.PIC24FJ64GB106-IPT.pdf
(352 pages)
4.PIC24FJ192GB108-IPT.pdf
(328 pages)
Specifications of PIC24FJ128GB106-I/PT
Core Size
16-Bit
Program Memory Size
128KB (43K x 24)
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART, USB OTG
Number Of I /o
51
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC24
No. Of I/o's
51
Ram Memory Size
16KB
Cpu Speed
32MHz
No. Of Timers
5
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
52
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Package
64TQFP
Device Core
PIC
Family Name
PIC24
Maximum Speed
32 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM183026 - KIT EVALUATION PIC16F/PIC24FDM240011 - KIT STARTER MPLAB FOR PIC24F MCUMA240014 - MODULE PLUG-IN PIC24
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ128GB106-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
19. Module: Memory (Program Space
20. Module: ICSP™
2010 Microchip Technology Inc.
When accessing data in the PSV area of data
RAM, it is possible to generate a false address
error trap condition by reading data located pre-
cisely at the lower address boundary (8000h). If
data is read using an instruction with an
auto-decrement, the resulting RAM address will be
below the PSV boundary (i.e., at 7FFEh); this will
result in an address error trap.
This false address error can also occur if a 32-bit
MOV instruction is used to read the data at location,
8000h.
Work around
Do not use the first location of the PSV page
(address 8000h). The MPLAB C Compiler (v3.11 or
later) supports the option, “-merrata=psv_trap”,
to prevent it from generating code that would cause
this erratum.
Affected Silicon Revisions
The
(RB5/RB4), cannot be used to read or program the
device.
Work around
Use either PGEC2/PGED2 or PGEC1/PGED1.
Affected Silicon Revisions
A3
A3
X
X
ICSP/ICD
A5
A5
Visibility)
port
pair,
PGEC3/PGED3
PIC24FJ256GB110 FAMILY
21. Module: Core (Instruction Set)
22. Module: RTCC
If an instruction producing a Read-After-Write stall
condition is executed inside a REPEAT loop, the
instruction will be executed fewer times than was
intended. For example, this loop:
repeat #0xf
inc [w1],[++w1]
will execute less than 15 times.
Work around
Avoid using REPEAT to repetitively execute
instructions that create a stall condition. Instead,
use a software loop using conditional branches.
The MPLAB C Compiler will not generate REPEAT
loops that cause this erratum.
Affected Silicon Revisions
Under certain circumstances, the value of the
Alarm Repeat Counter (ALCFGRPT<7:0>) may be
unexpectedly decremented. This happens only
when a byte write to the upper byte of ALCFGRPT
is performed in the interval between a device
POR/BOR, and the first edge from the RTCC clock
source.
Work around
Do not perform byte writes on ALCFGRPT,
particularly the upper byte.
Alternatively, wait until one period of the SOSC
has completed before performing byte writes to
ALCFGRPT.
Affected Silicon Revisions
A3
A3
X
X
A5
A5
X
DS80369K-page 7