DSPIC33FJ128GP802-I/MM Microchip Technology, DSPIC33FJ128GP802-I/MM Datasheet - Page 82

• Manufacturer Part Number: DSPIC33FJ128GP802-I/MM
• Description: IC DSPIC MCU/DSP 128K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP802-I/MM

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 28-QFN
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b, D/A 4x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Data Ram Size: 16 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
6.1
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 family of devices
have two types of Reset:
• Cold Reset
• Warm Reset
A cold Reset is the result of a Power-on Reset (POR)
or a Brown-out Reset (BOR). On a cold Reset, the
FNOSC configuration bits in the FOSC device
configuration register selects the device clock source.
A warm Reset is the result of all other reset sources,
including the RESET instruction. On warm Reset, the
device will continue to operate from the current clock
source as indicated by the Current Oscillator Selection
(COSC<2:0>)
(OSCCON<14:12>) register.
The device is kept in a Reset state until the system
power supplies have stabilized at appropriate levels
and the oscillator clock is ready. The sequence in
which this occurs is detailed below and is shown in
Figure 6-2.
1.
TABLE 6-1:
DS70292D-page 82
FRC, FRCDIV16,
FRCDIVN
FRCPLL
XT
HS
EC
XTPLL
HSPLL
ECPLL
SOSC
LPRC
Note 1:
Oscillator Mode
POR Reset: A POR circuit holds the device in
Reset when the power supply is turned on. The
POR circuit is active until V
threshold and the delay T
2:
3:
System Reset
T
times vary with crystal characteristics, load capacitance, etc.
T
10 MHz crystal and T
T
OSCD
OST
LOCK
bits
= Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, T
OSCILLATOR DELAY
= PLL lock time (1.5 ms nominal), if PLL is enabled.
= Oscillator Start-up Delay (1.1 s max for FRC, 70 s max for LPRC). Crystal Oscillator start-up
in
Startup Delay
Oscillator
the
POR
T
T
T
T
T
T
T
T
OSCD
OSCD
OSCD
OSCD
OSCD
OSCD
OSCD
OSCD
DD
—
—
OST
Oscillator
crosses the V
has elapsed.
= 32 ms for a 32 kHz crystal.
Control
Oscillator Startup
POR
Preliminary
Timer
T
T
T
T
T
OST
OST
OST
OST
OST
—
—
—
—
—
2.
3.
4.
5.
6.
BOR Reset: The on-chip voltage regulator has
a BOR circuit that keeps the device in Reset
until V
delay T
ensures that the voltage regulator output
becomes stable.
PWRT Timer: The programmable power-up
timer continues to hold the processor in Reset
for a specific period of time (T
BOR. The delay T
power supplies have stabilized at the appropri-
ate level for full-speed operation. After the delay
T
inactive, which in turn enables the selected
oscillator to start generating clock cycles.
Oscillator Delay: The total delay for the clock to
be ready for various clock source selections is
given in Table 6-1. Refer to Section 9.0
“Oscillator
information.
When the oscillator clock is ready, the processor
begins execution from location 0x000000. The
user application programs a GOTO instruction at
the reset address, which redirects program
execution to the appropriate start-up routine.
The Fail-safe clock monitor (FSCM), if enabled,
begins to monitor the system clock when the
system clock is ready and the delay T
elapsed.
PWRT
PLL Lock Time
DD
has elapsed, the SYSRST becomes
BOR
crosses the V
T
T
T
T
LOCK
LOCK
LOCK
LOCK
—
—
—
—
—
—
has elapsed. The delay T
Configuration”
PWRT
 2009 Microchip Technology Inc.
ensures that the system
BOR
T
T
OSCD
OSCD
OST
threshold and the
T
T
T
T
OSCD
Total Delay
= 102.4 s for a
OSCD
OSCD
OSCD
+ T
+ T
PWRT
T
T
T
OSCD
OSCD
for
LOCK
OST
OST
—
+ T
+ T
+ T
+ T
) after a
LOCK
+ T
+ T
OST
OST
OST
more
FSCM
BOR
LOCK
LOCK