PIC16F877A-I/P Microchip Technology, PIC16F877A-I/P Datasheet - Page 132
![IC MCU FLASH 8KX14 EE 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC16F877A-I/P
Manufacturer Part Number
PIC16F877A-I/P
Description
IC MCU FLASH 8KX14 EE 40DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16C770-ISO.pdf
(8 pages)
4.PIC16F873A-ISO.pdf
(234 pages)
5.PIC16F873A-ISO.pdf
(6 pages)
6.PIC16F873A-ISO.pdf
(4 pages)
7.PIC16F873A-ISO.pdf
(6 pages)
8.PIC16F873A-ISO.pdf
(4 pages)
9.PIC16F873A-ISO.pdf
(22 pages)
Specifications of PIC16F877A-I/P
Program Memory Type
FLASH
Program Memory Size
14KB (8K x 14)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
CCP/I2C/MSSP/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
33
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
444-1001 - DEMO BOARD FOR PICMICRO MCU
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
PIC16F877AI/P
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- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16F873A-ISO PDF datasheet #4
- PIC16F873A-ISO PDF datasheet #5
- PIC16F873A-ISO PDF datasheet #6
- PIC16F873A-ISO PDF datasheet #7
- PIC16F873A-ISO PDF datasheet #8
- PIC16F873A-ISO PDF datasheet #9
- Current page: 132 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
8.3
8.4
DS31008A-page 8-10
INSTRUCTION FLOW
Note 1: INTF flag is sampled here (every Q1).
GIE bit
(INTCON<7>)
INTF flag
(INTCON<1>)
CLKOUT
INT pin
OSC1
Instruction
executed
Instruction
fetched
PC
2: Interrupt latency = 3-4 T
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
Latency is the same whether Instruction (PC) is a single cycle or a 2-cycle instruction.
Interrupt Latency
INT and External Interrupts
3
Q1
Inst (PC-1)
Inst (PC)
Interrupt latency is defined as the time from the interrupt event (the interrupt flag bit gets set) to
the time that the instruction at address 0004h starts execution (when that interrupt is enabled).
For synchronous interrupts (typically internal), the latency is 3T
For asynchronous interrupts (typically external), such as the INT or Port RB Change Interrupt,
the interrupt latency will be 3 - 3.75T
when the interrupt event occurs
The latency is the same for both one and two cycle instructions.
The external interrupt on the INT pin is edge triggered: either rising if the INTEDG bit
(OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the INT
pin, the INTF flag bit (INTCON<1>) is set. This interrupt can be enabled/disabled by setting/clear-
ing the INTE enable bit (INTCON<4>). The INTF bit must be cleared in software in the interrupt
service routine before re-enabling this interrupt. The INT interrupt can wake-up the processor
from SLEEP, if the INTE bit was set prior to going into SLEEP. The status of the GIE bit decides
whether or not the processor branches to the interrupt vector following wake-up. See the
“Watchdog Timer and Sleep Mode”
from SLEEP through INT interrupt.
Figure 8-2: INT Pin and Other External Interrupt Timing
1
Q2
PC
Note:
Q3
4
CY
Q4
5
Any interrupts caused by external signals (such as timers, capture, change on port)
will have similar timing.
where T
Q1
Inst (PC+1)
Inst (PC)
CY
Q2
1
= instruction cycle time.
PC+1
Q3
Q4
(Figure
Interrupt Latency
Q1
Dummy Cycle
CY
section for details on SLEEP and for timing of wake-up
8-2) in relation to the instruction cycle.
Q2
PC+1
(instruction cycles). The exact latency depends upon
—
Q3
Q4
2
Q1
Dummy Cycle
Inst (0004h)
Q2
0004h
CY
Q3
.
1997 Microchip Technology Inc.
Q4
Q1
Inst (0005h)
Q2
Inst (0004h)
0005h
Q3
Q4
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