ATMEGA16L-8MU Atmel, ATMEGA16L-8MU Datasheet - Page 271

IC AVR MCU 16K 8MHZ 3V 44-QFN

ATMEGA16L-8MU

Manufacturer Part Number
ATMEGA16L-8MU
Description
IC AVR MCU 16K 8MHZ 3V 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA16L-8MU

Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
JTAG/SPI/UART
Total Internal Ram Size
1KB
# I/os (max)
32
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
MLF
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Reading the Signature
Bytes
Reading the
Calibration Byte
Parallel Programming
Characteristics
2466T–AVR–07/10
Figure 132. Mapping between BS1, BS2 and the Fuse- and Lock Bits during Read
The algorithm for reading the Signature bytes is as follows (refer to
page 266
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte ($00 - $02).
3. Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA.
4. Set OE to “1”.
The algorithm for reading the Calibration byte is as follows (refer to
page 266
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte, $00.
3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.
4. Set OE to “1”.
Figure 133. Parallel Programming Timing, Including some General Timing Requirements
(DATA, XA0/1, BS1, BS2)
for details on Command and Address loading):
for details on Command and Address loading):
Data & Contol
RDY/BSY
PAGEL
XTAL1
Fuse High Byte
Fuse Low Byte
WR
Lock Bits
BS2
t
t
BVPH
DVXH
t
t
XHXL
PHPL
0
1
t
t
t
t
XLDX
PLBX
XLWL
PLWL
t
BVWL
BS1
t
WL WH
WLRL
0
1
“Programming the Flash” on
“Programming the Flash” on
ATmega16(L)
DATA
t
WLBX
t
WLRH
271

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