ATMEGA16L-8PU Atmel, ATMEGA16L-8PU Datasheet - Page 235
![IC AVR MCU 16K 8MHZ 3V 40DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA16L-8PU
Manufacturer Part Number
ATMEGA16L-8PU
Description
IC AVR MCU 16K 8MHZ 3V 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA16L-8MI.pdf
(26 pages)
2.ATMEGA16L-8MI.pdf
(357 pages)
3.ATMEGA16-16PU.pdf
(358 pages)
Specifications of ATMEGA16L-8PU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
JTAG/SPI/UART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
A/d Inputs
8-Channel, 10-Bit
Cpu Speed
8 MIPS
Eeprom Memory
512 Bytes
Input Output
32
Interface
JTAG/SPI/UART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
16K Bytes
Timers
2-8-bit, 1-16-bit
Voltage, Range
2.7-5.5 V
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Scanning the Analog
Comparator
2466R–AVR–06/08
Figure 120. Boundary-scan Cells for Oscillators and Clock Options
Table 90
XTAL1/XTAL2 connections as well as 32 kHz Timer Oscillator.
Table 90. Scan Signals for the Oscillators
Notes:
The relevant Comparator signals regarding Boundary-scan are shown in
Boundary-scan cell from
described in
The Comparator need not be used for pure connectivity testing, since all analog inputs are
shared with a digital port pin as well.
Enable Signal
EXTCLKEN
OSCON
RCOSCEN
OSC32EN
TOSKON
1. Do not enable more than one clock source as main clock at a time.
2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between
3. The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock
Previous
From
Cell
summaries the scan registers for the external clock pin XTAL1, Oscillators with
the Internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is
preferred.
configuration is considered fixed for a given application. The user is advised to scan the same
clock option as to be used in the final system. The enable signals are supported in the scan
chain because the system logic can disable clock options in sleep modes, thereby disconnect-
ing the Oscillator pins from the scan path if not provided. The INTCAP Fuses are not
supported in the scan-chain, so the boundary scan chain can not make a XTAL Oscillator
requiring internal capacitors to run unless the fuse is correctly programmed.
ShiftDR
Table
0
1
ClockDR
RCCK
TOSCK
Scanned Clock Line
EXTCLK (XTAL1)
OSCCK
OSC32CK
91.
D
UpdateDR
Q
Next
Cell
To
Figure 122
D
G
Q
EXTEST
0
1
is attached to each of these signals. The signals are
Clock Option
External Clock
External Crystal
External Ceramic
Resonator
External RC
Low Freq. External Crystal
32 kHz Timer Oscillator
XTAL1/TOSC1
(1)(2)(3)
ENABLE
Oscillator
XTAL2/TOSC2
OUTPUT
Previous
Scanned Clock Line
when not Used
From
Cell
ATmega16(L)
ShiftDR
0
1
ClockDR
0
0
1
0
0
D
Figure
FF1
Q
Next
Cell
To
121. The
235
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