DSPIC33FJ64GS606-I/MR Microchip Technology, DSPIC33FJ64GS606-I/MR Datasheet - Page 4

• Manufacturer Part Number: DSPIC33FJ64GS606-I/MR
• Description: IC MCU/DSP 64KB FLASH 64QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64GS606-I/MR

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 64-VFQFN, Exposed Pad
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, QEI, POR, PWM, WDT
• Number Of I /o: 58
• Ram Size: 9K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Numeric And Arithmetic Format: Fixed-Point or Floating-Point
• Instruction Set Architecture: Harvard
• Device Million Instructions Per Second: 40 MIPs
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 58
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• On-chip Dac: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
6. Module: Interrupts
7. Module: ADC
DS80489C-page 4
When the dsPIC
mode, any interrupt should trigger the device to
exit Doze mode and generate an interrupt request
(IRQ) regardless of the interrupt priority level.
However, if the interrupt priority level is lower than
the CPU priority level, the interrupt request will not
be generated. As a result, the CPU will not detect
that it has exited Doze mode.
Work around
Any interrupt that is expected to wake the CPU
from Doze mode must be configured for an
interrupt priority level higher than the CPU priority
level. This work around can be implemented in
software right before the device enters Doze mode
and reverted to the desired priority level after it
wakes up from Doze mode.
Affected Silicon Revisions
If the ADC module is in an enabled state when the
device enters Sleep mode as a result of executing
a PWRSAV #0 instruction, the device power-down
current (I
in the device data sheet. This may happen even if
the ADC module is disabled by clearing the ADON
bit prior to entering Sleep mode.
Work around
In order to remain within the I
listed in the device data sheet, the user software
must completely disable the ADC module by
setting the ADC Module Disable bit in the
corresponding Peripheral Module Disable register
(PMDx), prior to executing a PWRSAV
instruction.
Affected Silicon Revisions
A0
A0
X
X
PD
) may exceed the specifications listed
®
DSC device is operating in Doze
PD
specifications
#0
8. Module: PWM
The External Period Reset mode is used to reset
the PWM period when the selected reset signal is
asserted during the OFF time of the PWM. If the
reset signal is asserted during the PWM ON time,
then the reset signal must be ignored.
However, on the dsPIC33FJ32GS406/606/608/
610
devices, the reset signal is not ignored at the end
of the PWM ON time. Therefore, the PWM period
will be reset immediately after the end of the PWM
ON time.
Work around
Ensure that the External Period Reset signal is
asserted during the PWM OFF time.
Affected Silicon Revisions
A0
X
and
dsPIC33FJ64GS406/606/608/610
© 2010 Microchip Technology Inc.