DSPIC30F4013-30I/PT Microchip Technology, DSPIC30F4013-30I/PT Datasheet - Page 10

• Manufacturer Part Number: DSPIC30F4013-30I/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-30I/PT

• Program Memory Type: FLASH
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Data Rom Size: 1024 B
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F401330IPT

dsPIC30F3014/4013
11. Module: I/O
12. Module: PLL
DS80455D-page 10
The I/O Port register values can be changed by
writing to the following address locations, which
are located in unimplemented memory space. A
write to these unimplemented addresses could
cause an I/O pin configured as an output to
change states. This state change could be
confirmed by reading either the PORT or LAT
register associated with the pin.
PORTB will be modified by a write to address 0x0C8
PORTC will be modified by a write to address 0x0CE
PORTD will be modified by a write to address 0x0D4
PORTE will be modified by a write to address 0x0DA
PORTF will be modified by a write to address 0x0E0
Work around
User software should avoid writing to the
unimplemented locations listed above.
Affected Silicon Revisions
When the 4x PLL mode of operation is selected, the
specified input frequency range of 4 MHz-10 MHz is
not fully supported.
When device V
frequency must be in the range of 4 MHz-5 MHz.
When device V
frequency must be in the range of 4 MHz-6 MHz
for both industrial and extended temperature
ranges.
Work around
1. Use 8x PLL or 16x PLL mode of operation and
2. Use the EC without PLL Clock mode with a
Affected Silicon Revisions
A1
A1
X
X
set final device clock speed using the
POST<1:0> oscillator postscaler control bits
(OSCCON<7:6>).
suitable clock frequency to obtain the equivalent
4x PLL clock rate.
A2
A2
X
X
DD
DD
is 2.5V-3.0V, the 4x PLL input
is 3.0V-3.6V, the 4x PLL input
13. Module: I
14. Module: INT0, ADC and Sleep Mode
15. Module: PLL
The SDA pin is the data pin for the I
This pin is multiplexed the RF2 pin. The state of
the LATF<2> overrides the SDA pin functionality
when LATF<2> is high. In order to use the I
module successfully, the LATF<2> bit must be low.
Work around
Before enabling the I
LATF<2> bit. The I
as long as this bit remains low.
Affected Silicon Revisions
ADC event triggers from the INT0 pin will not
wake-up the device from Sleep mode if the SMPI
bits are non-zero. This means that if the ADC is
configured to generate an interrupt after a certain
number of INT0 triggered conversions, the ADC
conversions will not be triggered and the device
will remain in Sleep. The ADC will perform
conversions and wake-up the device only if it is
configured to generate an interrupt after each INT0
triggered conversion (SMPI<3:0> = 0000).
Work around
None. If ADC event trigger from the INT0 pin is
required, initialize SMPI<3:0> to ‘0000’ (interrupt
on every conversion).
Affected Silicon Revisions
If 8x PLL mode is used, the input frequency range
is 5 MHz-10 MHz instead of 4 MHz-10 MHz.
Work around
None. If 8x PLL is used, make sure the input
crystal or clock frequency is 5 MHz or greater.
Affected Silicon Revisions
A1
A1
A1
X
X
X
A2
A2
A2
X
X
X
2
C
2
© 2010 Microchip Technology Inc.
C module will operate properly
2
C module, clear the
2
C module.
2
C