DSPIC30F4013-20I/PT Microchip Technology, DSPIC30F4013-20I/PT Datasheet - Page 115
![IC DSPIC MCU/DSP 48K 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
DSPIC30F4013-20I/PT
Manufacturer Part Number
DSPIC30F4013-20I/PT
Description
IC DSPIC MCU/DSP 48K 44TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F3014-30IPT.pdf
(228 pages)
2.DSPIC30F3014-30IPT.pdf
(16 pages)
3.DSPIC30F3014-30IPT.pdf
(6 pages)
4.DSPIC30F3014-30IPT.pdf
(14 pages)
5.DSPIC30F3014-30IPT.pdf
(20 pages)
6.DSPIC30F3014-20IP.pdf
(226 pages)
Specifications of DSPIC30F4013-20I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
30
Flash Memory Size
48KB
Supply Voltage Range
2.5V To 5.5V
Package
44TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
30
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
13-chx12-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F401320IPT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F4013-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F4013-20I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
• Receive Error Interrupts:
17.5
17.5.1
The CAN module has three transmit buffers. Each of
the three buffers occupies 14 bytes of data. Eight of the
bytes are the maximum 8 bytes of the transmitted mes-
sage. Five bytes hold the standard and extended
identifiers and other message arbitration information.
17.5.2
Transmit priority is a prioritization within each node of
the pending transmittable messages. There are
4 levels
(CiTXnCON<1:0>, where n = 0, 1 or 2, represents a
particular transmit buffer) for a particular message buf-
fer is set to ‘11’, that buffer has the highest priority. If
TXPRI<1:0> for a particular message buffer is set to
‘10’ or ‘01’, that buffer has an intermediate priority. If
TXPRI<1:0> for a particular message buffer is ‘00’, that
buffer has the lowest priority.
17.5.3
To initiate transmission of the message, the TXREQ bit
(CiTXnCON<3>) must be set. The CAN bus module
resolves any timing conflicts between setting of the
TXREQ bit and the Start-of-Frame (SOF), ensuring that if
the priority was changed, it is resolved correctly before the
SOF occurs. When TXREQ is set, the TXABT
(CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR
(CiTXnCON<4>) flag bits are automatically cleared.
2010 Microchip Technology Inc.
- Invalid Message Received:
- Receiver Overrun:
- Receiver Warning:
- Receiver Error Passive:
A receive error interrupt is indicated by the ERRIF
bit. This bit shows that an error condition
occurred. The source of the error can be deter-
mined by checking the bits in the CAN Interrupt
register, CiINTF.
If any type of error occurred during reception of
the last message, an error is indicated by the
IVRIF bit.
The RXnOVR bit indicates that an overrun
condition occurred.
The RXWAR bit indicates that the Receive Error
Counter (RERRCNT<7:0>) has reached the
warning limit of 96.
The RXEP bit indicates that the Receive Error
Counter has exceeded the error passive limit of
127 and the module has gone into error passive
state.
Message Transmission
of
TRANSMIT MESSAGE PRIORITY
TRANSMIT BUFFERS
TRANSMISSION SEQUENCE
transmit
priority.
If
TXPRI<1:0>
Setting TXREQ bit simply flags a message buffer as
enqueued for transmission. When the module detects
an available bus, it begins transmitting the message
which has been determined to have the highest priority.
If the transmission completes successfully on the first
attempt, the TXREQ bit is cleared automatically and an
interrupt is generated if TX1IE was set.
If the message transmission fails, one of the error
condition flags is set, and the TXREQ bit remains set,
indicating that the message is still pending for transmis-
sion. If the message encountered an error condition
during the transmission attempt, the TXERR bit is set,
and the error condition may cause an interrupt. If the
message loses arbitration during the transmission
attempt, the TXLARB bit is set. No interrupt is
generated to signal the loss of arbitration.
17.5.4
The system can also abort a message by clearing the
TXREQ bit associated with each message buffer.
Setting the ABAT bit (CiCTRL<12>) requests an abort
of all pending messages. If the message has not yet
started transmission, or if the message started but is
interrupted by loss of arbitration or an error, the abort is
processed. The abort is indicated when the module
sets the TXABT bit and the TXnIF flag is not
automatically set.
17.5.5
The CAN module detects the following transmission
errors:
• Acknowledge error
• Form error
• Bit error
These transmission errors do not necessarily generate
an interrupt but are indicated by the transmission error
counter. However, each of these errors causes the
transmission error counter to be incremented by one.
Once the value of the error counter exceeds the value
of 96, the ERRIF (CiINTF<5>) and the TXWAR bit
(CiINTF<10>) are set. Once the value of the error
counter exceeds the value of 96, an interrupt is
generated and the TXWAR bit in the Error Flag register
is set.
dsPIC30F3014/4013
ABORTING MESSAGE
TRANSMISSION
TRANSMISSION ERRORS
DS70138G-page 115