PIC24HJ128GP202-E/SP Microchip Technology, PIC24HJ128GP202-E/SP Datasheet - Page 32

• Manufacturer Part Number: PIC24HJ128GP202-E/SP
• Description: IC PIC MCU FLASH 128K 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ128GP202-E/SP

• Core Size: 16-Bit
• Program Memory Size: 128KB (43K x 24)
• Core Processor: PIC
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC24
• No. Of I/o's: 21
• Ram Memory Size: 8192Byte
• Cpu Speed: 7.37MHz
• No. Of Timers: 7
• Interface: I2C, SPI, USART
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164337 - MODULE SOCKET FOR PM3 40DIP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

5.0
ICSP mode is a special programming protocol that
allows you to read and write to dsPIC33F/PIC24H
device family memory. The ICSP mode is the most
direct method used to program the device; however,
note that Enhanced ICSP is faster. ICSP mode also
has the ability to read the contents of executive
memory to determine if the programming executive is
present. This capability is accomplished by applying
control codes and instructions serially to the device
using pins PGCx and PGDx.
In ICSP mode, the system clock is taken from the
PGCx pin, regardless of the device’s oscillator Config-
uration bits. All instructions are shifted serially into an
internal buffer, then loaded into the instruction register
and executed. No program fetching occurs from inter-
nal memory. Instructions are fed in 24 bits at a time.
PGDx is used to shift data in, and PGCx is used as both
the serial shift clock and the CPU execution clock.
DS70152H-page 32
Note:
Note:
DEVICE PROGRAMMING – ICSP
Any development tool that modifies the con-
figuration memory on dsPIC33FJ06GS101/
102/202,
504, dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610 devices
must take care to preserve the data con-
tained in the last six words of program mem-
ory. Refer to
Calibration
information.
During ICSP operation, the operating
frequency of PGCx must not exceed
5 MHz.
Appendix C: “Diagnostic and
dsPIC33FJ16GS402/404/502/
Registers”
for
more
5.1
Figure 5-1
programming process. After entering ICSP mode, the
first action is to Bulk Erase the device. Next, the code
memory is programmed, followed by the device
Configuration registers. Code memory (including the
Configuration registers) is then verified to ensure that
programming was successful. Then, program the
code-protect Configuration bits, if required.
FIGURE 5-1:
Overview of the Programming
Process
illustrates the high-level overview of the
Program Configuration Bits
Verify Configuration Bits
Program Memory
Verify Program
Enter ICSP™
Perform Bulk
Exit ICSP
HIGH-LEVEL ICSP™
PROGRAMMING FLOW
© 2010 Microchip Technology Inc.
Erase
Start
End