PIC16LF84-04I/SO Microchip Technology, PIC16LF84-04I/SO Datasheet - Page 12

• Manufacturer Part Number: PIC16LF84-04I/SO
• Description: IC MCU FLASH 1KX14 EE 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF84-04I/SO

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Oscillator Type: External
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 68 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC16LF
• No. Of I/o's: 13
• Eeprom Memory Size: 64Byte
• Ram Memory Size: 68Byte
• Cpu Speed: 4MHz
• No. Of: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC16LC84A-04I/SO

PIC16C84
4.2
The data memory is partitioned into two areas. The first
is the Special Function Registers (SFR) area, while the
second is the General Purpose Registers (GPR) area.
The SFRs control the operation of the device.
Portions of data memory are banked. This is for both
the SFR area and the GPR area. The GPR area is
banked to allow greater than 116 bytes of general
purpose RAM. The banked areas of the SFR are for the
registers that control the peripheral functions. Banking
requires the use of control bits for bank selection.
These control bits are located in the STATUS Register.
Figure 4-2 shows the data memory map organization.
Instructions MOVWF and MOVF can move values from the
W register to any location in the register file (“F”), and
vice-versa.
The entire data memory can be accessed either
directly using the absolute address of each register file
or indirectly through the File Select Register (FSR)
(Section 4.5). Indirect addressing uses the present
value of the RP1:RP0 bits for access into the banked
areas of data memory.
Data memory is partitioned into two banks which
contain the general purpose registers and the special
function registers. Bank 0 is selected by clearing the
RP0 bit (STATUS<5>). Setting the RP0 bit selects
Bank 1. Each Bank extends up to 7Fh (128 bytes). The
first twelve locations of each Bank are reserved for the
Special Function Registers. The remainder are Gen-
eral Purpose Registers implemented as static RAM.
4.2.1
All devices have some amount of General Purpose
Register (GPR) area. Each GPR is 8 bits wide and is
accessed either directly or indirectly through the FSR
(Section 4.5).
The GPR addresses in bank 1 are mapped to
addresses in bank 0. As an example, addressing loca-
tion 0Ch or 8Ch will access the same GPR.
4.2.2
The Special Function Registers (Figure 4-2 and
Table 4-1) are used by the CPU and Peripheral
functions to control the device operation. These
registers are static RAM.
The special function registers can be classified into two
sets, core and peripheral. Those associated with the
core functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for that specific feature.
DS30445C-page 12
Data Memory Organization
GENERAL PURPOSE REGISTER FILE
SPECIAL FUNCTION REGISTERS
FIGURE 4-2:
File Address
Note 1:
Unimplemented data memory location; read as '0'.
0Ch
0Ah
0Bh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
2Fh
30h
7Fh
Not a physical register.
Indirect addr.
PCLATH
INTCON
registers
STATUS
EEDATA
Purpose
General
(SRAM)
PORTB
EEADR
PORTA
Bank 0
TMR0
FSR
PCL
36
REGISTER FILE MAP
(1)
1997 Microchip Technology Inc.
Indirect addr.
EECON2
EECON1
OPTION
STATUS
PCLATH
INTCON
(accesses)
TRISA
TRISB
in Bank 0
Bank 1
Mapped
FSR
PCL
(1)
(1)
File Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
AFh
B0h
FFh