PIC24FJ128GA110-I/PT Microchip Technology, PIC24FJ128GA110-I/PT Datasheet - Page 7

• Manufacturer Part Number: PIC24FJ128GA110-I/PT
• Description: IC PIC MCU FLASH 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ128GA110-I/PT

• Core Size: 16-Bit
• Program Memory Size: 128KB (43K x 24)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC24
• No. Of I/o's: 85
• Ram Memory Size: 16KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDMA240015 - BOARD MCV PIM FOR 24F256GADM240011 - KIT STARTER MPLAB FOR PIC24F MCU
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

18. Module: I
19. Module: I
 2010 Microchip Technology Inc.
Under certain circumstances, a module operating
in Master mode may Acknowledge its own com-
mand addressed to a slave device. This happens
when the following occurs:
• 10-Bit Addressing mode is used (A10M = 1),
• the I
In these cases, the master also Acknowledges the
address command and generates an erroneous I
slave interrupt, as well as the I
Work around
Several options are available:
• When using 10-Bit Addressing mode, make
If this cannot be avoided:
• Clear the A10M bit (I2CxCON<10> = 0) prior to
• Read the ADD10 bit (I2CxSTAT<8>) to check
Affected Silicon Revisions
Under certain circumstances, a module operating
in Slave mode may not respond correctly to some
of the special addresses reserved by the I
protocol. This happens when the following occurs:
• 10-Bit Addressing mode is used (A10M = 1),
• bits, A<7:1>, of the Slave address
In these cases, the Slave module Acknowledges
the command and triggers an I
does not copy the data into the I2CxRCV register
or set the RBF bit.
Work around
Do not set bits, A<7:1>, of the module’s slave
address equal to ‘1111xxx’ or ‘0000xxx’.
Affected Silicon Revisions
A3
A3
and:
address bits (I2CADD<9:8>) as the addressed
slave module.
certain that the master and slave devices do not
share the same 2 MSBs of their addresses.
performing a Master mode transmit.
for a full 10-bit match whenever a slave I
interrupt occurs on the master module.
X
and
(I2CADD<7:1>) fall into the range of the
reserved 7-bit address ranges, ‘1111xxx’ or
‘0000xxx’.
X
2
C master has the same two upper
A5
A5
2
2
C™ Module (Master Mode)
C Module (Slave Mode)
2
2
C master interrupt.
C slave interrupt; it
PIC24FJ256GA110 FAMILY
2
C
2
2
C
C
20. Module: A/D Converter
21. Module: SPI (Enhanced Buffer Mode)
Note:
When using PGEC1 and PGED1 to debug an
application on any 64-pin devices in this family, all
voltage references will be disabled. This includes
V
will always equal 3FFh.
Work around
Use PGEC2 and PGED2 to debug any A/D
functionality.
Affected Silicon Revisions
In Enhanced Master mode, the SRMPT bit
(SPIxSTAT<7>) may erroneously become set for
several clock cycles in the middle of a FIFO transfer,
indicating that the shift register is empty when it is
not. This happens when both SPI clock prescalers
are set to values other than their maximum
(SPIxCON<4:2> ≠ 000 and SPIxCON<1:0> ≠ 00).
Work around
Configure the module to generate an SPI event
interrupt whenever the last bit is shifted out of the
shift register (SPIxSTAT<4:2> = 101). When the
SPIxIF flag becomes set, the shift register is
empty.
Affected Silicon Revisions
REF
A3
A3
X
X
+, V
This issue applies only to 64-pin devices in
this
PIC24FJ192GA106
PIC24FJ128GA106).
A5
A5
REF
-, AV
family
DD
and AV
SS
(PIC24FJ256GA106,
. Any A/D conversion
DS80368J-page 7
and