DSPIC30F4013-20I/ML Microchip Technology, DSPIC30F4013-20I/ML Datasheet - Page 100
![IC DSPIC MCU/DSP 48K 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC30F4013-20I/ML
Manufacturer Part Number
DSPIC30F4013-20I/ML
Description
IC DSPIC MCU/DSP 48K 44QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F3014-30IPT.pdf
(228 pages)
2.DSPIC30F3014-30IPT.pdf
(16 pages)
3.DSPIC30F3014-30IPT.pdf
(6 pages)
4.DSPIC30F3014-30IPT.pdf
(14 pages)
5.DSPIC30F3014-30IPT.pdf
(20 pages)
6.DSPIC30F3014-20IP.pdf
(226 pages)
Specifications of DSPIC30F4013-20I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
30
Flash Memory Size
48KB
Supply Voltage Range
2.5V To 5.5V
Package
44QFN EP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
30
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
13-chx12-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F401320IML
- DSPIC30F3014-30IPT PDF datasheet
- DSPIC30F3014-30IPT PDF datasheet #2
- DSPIC30F3014-30IPT PDF datasheet #3
- DSPIC30F3014-30IPT PDF datasheet #4
- DSPIC30F3014-30IPT PDF datasheet #5
- DSPIC30F3014-20IP PDF datasheet #6
- Current page: 100 of 226
- Download datasheet (4Mb)
dsPIC30F3014/4013
15.2
The module supports a basic framed SPI protocol in
Master or Slave mode. The control bit, FRMEN,
enables framed SPI support and causes the SSx pin to
perform the Frame Synchronization pulse (FSYNC)
function. The control bit, SPIFSD, determines whether
FIGURE 15-1:
FIGURE 15-2:
DS70138F-page 98
Note: x = 1 or 2, y = 1 or 2.
Framed SPI Support
Note: x = 1 or 2.
SDOx
SCKx
SDIx
SSx
MSb
PROCESSOR 1
SPI BLOCK DIAGRAM
SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
SPI Master
SSx and
Shift Register
FSYNC
Control
(SPIxBUF)
Receive
(SPIxSR)
SPIxBUF
Read
bit 0
SPIxSR
LSb
Control
Clock
SDOx
SCKx
SDIx
Clock
Shift
SPIxBUF
Write
Transmit
Serial Clock
Data Bus
Internal
Select
Edge
the SSx pin is an input or an output (i.e., whether the
module receives or generates the Frame Synchroniza-
tion pulse). The frame pulse is an active-high pulse for
a single SPI clock cycle. When Frame Synchronization
is enabled, the data transmission starts only on the
subsequent transmit edge of the SPI clock.
SDOy
SCKy
SDIy
Enable Master Clock
Secondary
Prescaler
1:1-1:8
MSb
Serial Input Buffer
Shift Register
PROCESSOR 2
(SPIyBUF)
(SPIySR)
SPI Slave
© 2008 Microchip Technology Inc.
Prescaler
1:16, 1:64
1:1, 1:4,
Primary
LSb
F
CY
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