PIC24HJ64GP510-I/PT Microchip Technology, PIC24HJ64GP510-I/PT Datasheet - Page 13
![IC PIC MCU FLASH 32KX16 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC24HJ64GP510-I/PT
Manufacturer Part Number
PIC24HJ64GP510-I/PT
Description
IC PIC MCU FLASH 32KX16 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ64GP206-IPT.pdf
(292 pages)
3.PIC24HJ64GP206-IPT.pdf
(8 pages)
4.PIC24HJ64GP206-IPT.pdf
(20 pages)
5.PIC24HJ64GP206-IPT.pdf
(26 pages)
6.PIC24HJ128GP306-IPT.pdf
(288 pages)
Specifications of PIC24HJ64GP510-I/PT
Core Size
16-Bit
Program Memory Size
64KB (22K x 24)
Core Processor
PIC
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Controller Family/series
PIC24
No. Of I/o's
85
Ram Memory Size
8KB
Cpu Speed
40MIPS
No. Of Timers
13
No. Of Pwm Channels
8
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN, I2C, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Number Of Timers
13
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 32 Channel
A/d Bit Size
12 bit
A/d Channels Available
32
Height
1 mm
Length
12 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Width
12 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDAC164333 - MODULE SKT FOR PM3 100QFPDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24HJ64GP510-I/PT
Manufacturer:
Microchip
Quantity:
104
Company:
Part Number:
PIC24HJ64GP510-I/PT
Manufacturer:
MICROCHIP
Quantity:
455
Company:
Part Number:
PIC24HJ64GP510-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
33. Module: DMA
34. Module: Doze Mode and Traps
35. Module: Output Compare
© 2008 Microchip Technology Inc.
When a DMA channel is enabled in Single-Shot
mode while the device is in Idle mode, and the
corresponding peripheral is active and configured
to operate during Idle mode, the DMA channel
may not become disabled immediately upon
transferring the required amount of data.
As a result, the number of bytes or words of data
transferred may exceed the DMA transfer count
specified in the DMAxCNT register.
For example, if DMA transfers are active for both
SPI byte transmissions and receptions, and only
the receive DMA channel interrupt is enabled for
waking up the device from Idle mode, an extra byte
will be transmitted by the time the device wakes up
from Idle mode.
Work around
None.
A DMA error trap may not be generated when the
device is in Doze mode.
Work around
None.
When the Output Compare module is operated in
the Dual Compare Match mode, a timer compare
match with the value in the OCxR register sets the
OCx output producing a rising edge on the OCx
pin. Then, when a timer compare match with the
value in the OCxRS register occurs, the OCx
output is reset producing a falling edge on the OCx
pin.
The above statement applies to all conditions
except when the difference between OCxR and
OCxRS is 1. In this case, the Output Compare
module may miss the reset compare event, and
cause the OCx pin to remain continuously high.
This condition will remain until the difference
between values in the OCxR and OCxRS registers
is made greater than 1.
Work around
Ensure in software that the difference between
values in OCxR and OCxRS registers is
maintained greater than 1.
PIC24HJXXXGPX06/X08/X10
36. Module: UART
37. Module: UART
38. Module: DMA
39. Module: DMA
When the UART is in 4x mode (BRGH = 1) and
using two Stop bits (STSEL = 1), it may sample the
first Stop bit instead of the second one.
This issue does not affect the other UART
configurations.
Work around
Use the 16x baud rate option (BRGH = 0) and
adjust the baud rate accordingly.
When an auto-baud is detected, the receive
interrupt may occur twice. The first interrupt occurs
at the beginning of the Start bit and the second
after reception of the Sync field character.
Work around
If an extra interrupt is detected, ignore the
additional interrupt.
When the DMA channel is configured for NULL
Data
(DMAxCON<11> = 1), it does not execute a null
(all zeros) write to the peripheral address.
Work around
Use two DMA channels to receive data from the
peripheral
configured to transfer data from the peripheral to
DMA RAM, while another channel must be
configured to transfer dummy data from the DMA
RAM to the peripheral. Both channels must be
setup for the same DMA request.
A low priority DMA channel request can be
pre-empted by a higher priority DMA channel
request. For example, if DMA Channel 0 has a
higher priority than DMA Channel 1. A request
to DMA channel 1 will be pending while DMA
Channel 0 is processing its request. If DMA
Channel 1 receives another request while it is in
a pending request state, the DMA module does
not generate a DMA error trap event.
Work around
None. Using higher priority DMA channels for
servicing sources of frequent requests significantly
reduces the possibility of the condition described
above occurring, but does not completely
eliminate it.
module.
Peripheral
One
channel
Write
DS80280G-page 13
must
mode
be