PIC16C774/P Microchip Technology, PIC16C774/P Datasheet - Page 71

• Manufacturer Part Number: PIC16C774/P
• Description: IC MCU OTP 4KX14 A/D PWM 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C774/P

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC16C
• No. Of I/o's: 33
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING444-1001 - DEMO BOARD FOR PICMICRO MCU
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC16C774-04/P; PIC16C774-20/P

8.2.5
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a reset or when the MSSP module is dis-
abled. Control of the I
bit is set, or the bus is idle with both the S and P bits
clear.
FIGURE 8-17: SSP BLOCK DIAGRAM (I
1999 Microchip Technology Inc.
SDA
SCL
MASTER MODE
2
C bus may be taken when the P
SDA in
Bus Collision
SCL in
Read
Advance Information
MSb
Write collision detect
end of XMIT/RCV
Start bit, Stop bit,
Clock Arbitration
State counter for
Start bit detect,
2
Stop bit detect
Acknowledge
C MASTER MODE)
Generate
SSPBUF
SSPSR
LSb
Write
In master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
clock
data bus
shift
Internal
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset AKSTAT, PEN (SSPCON2)
PIC16C77X
SSPADD<6:0>
SSPM3:SSPM0,
Baud
rate
generator
DS30275A-page 71