PIC16F876-20/SP Microchip Technology, PIC16F876-20/SP Datasheet - Page 173

• Manufacturer Part Number: PIC16F876-20/SP
• Description: IC MCU FLASH 8KX14 EE 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F876-20/SP

• Program Memory Type: FLASH
• Program Memory Size: 14KB (8K x 14)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: MSSP/PSP/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
• Minimum Operating Temperature: 0 C
• On-chip Adc: 5-ch x 10-bit
• Data Rom Size: 256 B
• A/d Bit Size: 10 bit
• A/d Channels Available: 5
• Height: 3.3 mm
• Length: 34.67 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4 V
• Width: 7.24 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

11.4
1997 Microchip Technology Inc.
GIE bit
INSTRUCTION
FLOW
T0IF bit
Instruction
fetched
Instruction
executed
Timer0
CLKOUT(3)
OSC1
PC
TMR0 Interrupt
Note 1: Interrupt flag bit T0IF is sampled here (every Q1).
Q1
2: Interrupt latency = 4T
3: CLKOUT is available only in RC oscillator mode.
FEh
Inst (PC)
Inst (PC-1)
Q2
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This
overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE
(INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service rou-
tine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut-off during SLEEP. See
Figure 11-4: TMR0 Interrupt Timing
1
PC
Q3
Q4
CY
Q1
FFh
where T
Inst (PC+1)
Inst (PC)
Q2
1
PC +1
CY
Q3
= instruction cycle time.
Q4
Q1
00h
Dummy cycle
Q2
PC +1
Q3
Section 11. Timer0
Q4
Figure 11-4
Q1
01h
Dummy cycle
Inst (0004h)
Q2
0004h
Q3
for Timer0 interrupt timing.
Q4
Q1
DS31011A-page 11-5
02h
Inst (0004h)
Inst (0005h)
Q2
0005h
Q3
Q4
11