PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 5

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.1.1
The microcontroller core of PIC18F97J60 family
devices can be powered either from an external
source, or from an on-chip regulator, which derives
power from V
V
The regulator is enabled by connecting V
ENVREG pin. In this case, a low-ESR capacitor must
be connected to the V
device operation. If the regulator is disabled, power to
the core must be supplied on V
V
supplied separately on V
shown in Figure 2-4. Whether or not the regulator is
used, it is always good design practice to have
sufficient capacitance on all supply pins.
The specifications for core voltage and capacitance are
listed in Section 6.0 “AC/DC Characteristics and
Timing Requirements”.
FIGURE 2-4:
2.2
PIC18F97J60 family devices are available in three
program memory sizes: 64 Kbytes, 96 Kbytes and
128 Kbytes. The overall memory maps for all devices
are shown in Figure 2-5.
© 2009 Microchip Technology Inc.
DDCORE
DD
(V
(V
exceeds V
Regulator Disabled (ENVREG Tied to Ground):
DD
DD
Regulator Enabled (ENVREG Tied to V
> V
Memory Maps
= V
/V
CAP
ON-CHIP VOLTAGE REGULATOR
DDCORE
DDCORE
DD
DDCOREMAX
pin.
C
F
. Both sources use the common
3.3V
)
)
2.5V 3.3V
CONNECTIONS FOR THE
ON-CHIP REGULATOR
2.5V
DDCORE
DDCORE
PIC18FXXJ60/65
V
V
V
ENVREG
, power to the core must be
DD
DDCORE
SS
PIC18FXXJ60/65
/V
V
V
V
DDCORE
PIC18FXXJ60/65
ENVREG
V
ENVREG
V
V
/V
DD
DDCORE
SS
DD
DDCORE
SS
CAP
/V
CAP
CAP
. Examples are
pin for proper
/V
/V
/V
CAP
CAP
CAP
DD
DD
):
. Where
to the
PIC18F97J60 FAMILY
For purposes of code protection, the program memory
for every device is treated as a single block. Enabling
code protection thus protects the entire code memory
and not individual segments.
The Configuration Words for these devices are located
at addresses 300000h through 300005h. These are
implemented as three pairs of volatile memory
registers. Each register is automatically loaded from a
copy stored at the end of program memory. For this
reason, the last four words of the code space (also
called the Flash Configuration Words) should be
written with configuration data and not executable
code. The addresses of the Flash Configuration Words
are also listed in Table 2-2. Refer to Section 5.0
“Configuration Word” for more information.
Locations 3FFFFEh and 3FFFFFh are reserved for the
device ID bits. These bits may be used by the program-
mer to identify what device type is being programmed
and are described in Section 5.1 “Device ID Word”.
These device ID bits read out normally, even after code
protection.
TABLE 2-2:
2.2.1
Memory in the device address space (000000h to
3FFFFFh) is addressed via the Table Pointer register,
which in turn is comprised of three registers:
• TBLPTRU at RAM address 0FF8h
• TBLPTRH at RAM address 0FF7h
• TBLPTRL at RAM address 0FF6h
The 4-bit command, ‘0000’ (core instruction), is used to
load the Table Pointer prior to using many read or write
operations.
PIC18F66J60
PIC18F86J60
PIC18F96J60
PIC18F66J65
PIC18F86J65
PIC18F96J65
PIC18F67J60
PIC18F87J60
PIC18F97J60
Addr[21:16]
TBLPTRU
Device
MEMORY ADDRESS POINTER
PROGRAM MEMORY SIZES
FOR PIC18F97J60 FAMILY
DEVICES
TBLPTRH
Addr[15:8]
Program
(Kbytes)
Memory
128
64
96
1FFF8h:1FFFFh
17FF8h:17FFFh
DS39688D-page 5
Configuration
FFF8h:FFFFh
Location of
TBLPTRL
Addr[7:0]
Words
Flash