ATMEGA3250P-20AU Atmel, ATMEGA3250P-20AU Datasheet
ATMEGA3250P-20AU
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ATMEGA3250P-20AU Summary of contents
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... I/O and Packages – 54/69 Programmable I/O Lines – 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP • Speed Grade: – ATmega325PV/ATmega3250PV MHz @ 1.8 - 5.5V MHz @ 2.7 - 5.5V – ATmega325P/3250P MHz @ 2.7 - 5.5V MHz @ 4.5 - 5.5V • Temperature range: – -40°C to 85°C Industrial • ...
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... Pin Configurations Figure 1-1. ATmega325P/3250P 2 Pinout ATmega3250P DNC 1 2 (RXD/PCINT0) PE0 INDEX CORNER (TXD/PCINT1) PE1 3 4 (XCK/AIN0/PCINT2) PE2 (AIN1/PCINT3) PE3 5 6 (USCK/SCL/PCINT4) PE4 (DI/SDA/PCINT5) PE5 7 8 (DO/PCINT6) PE6 (CLKO/PCINT7) PE7 9 10 VCC GND 11 12 DNC (PCINT24) PJ0 13 14 (PCINT25) PJ1 DNC ...
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Figure 1-2. Note: 1.1 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 2. ...
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Block Diagram Figure 2-1. Block Diagram GND VCC DATA REGISTER PORTF AVCC AGND AREF JTAG TAP ON-CHIP DEBUG BOUNDARY- SCAN PROGRAMMING LOGIC USART DATA REGISTER PORTE The AVR core combines a rich instruction set with 32 general purpose working ...
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... The ATmega325P/3250P AVR is supported with a full suite of program and system develop- ment tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 2.2 Comparison between ATmega325P and ATmega3250P The ATmega325P and ATmega3250P differs only in memory sizes, pin count and pinout. 2-1 on page 5 Table 2-1. Device ATmega325P ATmega3250P 8023FS– ...
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Pin Descriptions The following section describes the I/O-pin special functions. 2.3 Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7..PA0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ...
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... As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special features of the ATmega3250P as listed on page 75. ...
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RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Characterizations” on page 2.3.13 XTAL1 ...
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... Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 8023FS–AVR–07/09 ATmega325P/3250P 9 ...
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Note: 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 5. About Code Examples This documentation contains simple code ...
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... Reserved - (0xD2) Reserved - (0xD1) Reserved - (0xD0) Reserved - (0xCF) Reserved - (0xCE) Reserved - (0xCD) Reserved - (0xCC) Reserved - (0xCB) Reserved - (0xCA) Reserved - (0xC9) Reserved - (0xC8) Reserved - (0xC7) UDR0 (0xC6) UBRR0H (0xC5) 8023FS–AVR–07/09 Registers with bold type only available in ATmega3250P. Bit 6 Bit 5 Bit ...
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Address Name Bit 7 UBRR0L (0xC4) Reserved - (0xC3) UCSR0C - (0xC2) UCSR0B RXCIE0 (0xC1) UCSR0A RXC0 (0xC0) Reserved - (0xBF) Reserved - (0xBE) Reserved - (0xBD) Reserved - (0xBC) Reserved - (0xBB) USIDR (0xBA) USISR USISIF (0xB9) USICR USISIE ...
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Address Name Bit 7 TCNT1H (0x85) TCNT1L (0x84) Reserved - (0x83) TCCR1C FOC1A (0x82) TCCR1B ICNC1 (0x81) TCCR1A COM1A1 (0x80) DIDR1 - (0x7F) DIDR0 ADC7D (0x7E) Reserved - (0x7D) ADMUX REFS1 (0x7C) ADCSRB - (0x7B) ADCSRA ADEN (0x7A) ADCH (0x79) ...
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Address Name Bit 7 TCNT0 0x26 (0x46) Reserved - 0x25 (0x45) TCCR0A FOC0A 0x24 (0x44) GTCCR TSM 0x23 (0x43) EEARH - 0x22 (0x42) EEARL 0x21 (0x41) EEDR 0x20 (0x40) EECR - 0x1F (0x3F) GPIOR0 0x1E (0x3E) EIMSK PCIE3 0x1D (0x3D) ...
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Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...
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Mnemonics Operands BRVC k Branch if Overflow Flag is Cleared BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register CBI P,b Clear Bit in I/O Register ...
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Mnemonics Operands PUSH Rr Push Register on Stack POP Rd Pop Register from Stack MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break 8023FS–AVR–07/09 Description STACK ← ← STACK (see specific descr. for Sleep ...
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... Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. ...
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... Figure 26-1 on page 306 CC 100A 100-lead 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 8023FS–AVR–07/09 (2) Ordering Code Package Type ATmega3250PV-10AU ATmega3250P-20AU and Figure 26-2 on page 306. Package Type ATmega325P/3250P (1) Operational Range Industrial 100A 0⋅C to 85⋅C) ...
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Packaging Information 31.1 64A PIN 0°~7° L Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 ...
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Marked Pin TOP VIEW BOTTOM VIEW Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. 2325 Orchard Parkway San Jose, CA 95131 R ...
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PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 ...
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Errata 32.1 ATmega325P rev. A • Interrupts may be lost when writing the timer registers in the asynchronous timer. • Using BOD disable will make the chip reset. 1. Interrupts may be lost when writing the timer registers in ...
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... Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 32.6 ATmega3250P rev. C • Interrupts may be lost when writing the timer registers in the asynchronous timer. 1. Interrupts may be lost when writing the timer registers in the asynchronous timer. ...
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... Updated DEVICE and JTAG ID in Updated ”System and Reset Characterizations” on page Updated ”Typical Characteristics” on page 314 Initial version. ATmega325P/3250P 15. 32. ”External Interrupts” on page 85. 308. and ”ATmega3250P rev. C” on 274. Table 25-6 on page 274 308. 58. 147. 356 ...