ATMEGA3250PV-10AU Atmel, ATMEGA3250PV-10AU Datasheet - Page 241

• Manufacturer Part Number: ATMEGA3250PV-10AU
• Description: IC MCU AVR 32K FLASH 100-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA3250PV-10AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, USI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Data Rom Size: 1 KB
• Operating Supply Voltage: 1.8 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Height: 1 mm
• Length: 14 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Width: 14 mm
• For Use With: ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK504 - STARTER KIT AVR EXP MOD 100P LCD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA3250PV-8AU; ATMEGA3250PV-8AU

23.6
8023F–AVR–07/09
ATmega325P/3250P Boundary-scan Order
Table 23-6
scan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit
scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of
Port A is scanned in the opposite bit order of the other ports. Exceptions from the rules are the
Scan chains for the analog circuits, which constitute the most significant bits of the scan chain
regardless of which physical pin they are connected to. In
to FF0, PXn. Control corresponds to FF1, and PXn. Pull-up_enable corresponds to FF2. Bit 4, 5,
6 and 7 of Port F is not in the scan chain, since these pins constitute the TAP pins when the
JTAG is enabled.
Table 23-6.
Bit Number
197
196
195
194
and
ATmega325P Boundary-scan Order, 64-pin
Table 23-7
Signal Name
AC_IDLE
ACO
ACME
AINBG
shows the Scan order between TDI and TDO when the Boundary-
Module
Comparator
ATmega325P/3250P
Figure
23-2, PXn. Data corresponds
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