PIC16F873-20I/SO Microchip Technology, PIC16F873-20I/SO Datasheet - Page 244
![IC MCU FLASH 4KX14 EE 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC16F873-20I/SO
Manufacturer Part Number
PIC16F873-20I/SO
Description
IC MCU FLASH 4KX14 EE 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F873-04SO.pdf
(218 pages)
4.PIC16F873-04SO.pdf
(5 pages)
5.PIC16F873-04SO.pdf
(5 pages)
6.PIC16F873-04SO.pdf
(4 pages)
Specifications of PIC16F873-20I/SO
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
PIC16F
No. Of I/o's
22
Eeprom Memory Size
128Byte
Ram Memory Size
192Byte
Cpu Speed
20MHz
No. Of Timers
3
Package
28SOIC W
Device Core
PIC
Family Name
PIC16
Maximum Speed
20 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
22
Interface Type
I2C/SPI/USART
On-chip Adc
5-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL309-1073 - ADAPTER 28-SOIC TO 28-SOIC309-1024 - ADAPTER 28-SOIC TO 28-DIP309-1023 - ADAPTER 28-SOIC TO 28-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F873-20I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F873-04SO PDF datasheet #3
- PIC16F873-04SO PDF datasheet #4
- PIC16F873-04SO PDF datasheet #5
- PIC16F873-04SO PDF datasheet #6
- Current page: 244 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
15.4.1.4
15.4.2
15.4.3
DS31015A-page 15-24
Clock Arbitration
Master Mode (Firmware)
Multi-Master Mode (Firmware)
Clock arbitration has the SCL pin to inhibit the master device from sending the next clock pulse.
The SSP module in I
to the SSP interrupt (SSPIF bit is set and the CKP bit is cleared). The data that needs to be trans-
mitted will need to be written to the SSPBUF register, and then the CKP bit will need to be set to
allow the master to generate the required clocks.
Master mode of operation is supported by interrupt generation on the detection of the START and
STOP conditions. The STOP (P) and START (S) bits are cleared from a reset or when the SSP
module is disabled. Control of the I
with both the S and P bits clear.
In master mode the SCL and SDA lines are manipulated by clearing the corresponding TRIS
bit(s). The output level is always low, irrespective of the value(s) in the PORT register. So when
transmitting data, a '1' data bit must have it’s TRIS bit set (input) and a '0' data bit must have it’s
TRIS bit cleared (output). The same scenario is true for the SCL line with the TRIS bit.
The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
Master mode of operation can be done with either the slave mode idle (SSPM3:SSPM0 = 1011)
or with the slave active (SSPM3:SSP0 = 1110 or 1111). When the slave modes are enabled, the
software needs to differentiate the source(s) of the interrupt.
In multi-Master mode, the interrupt generation on the detection of the START and STOP condi-
tions allows the determination of when the bus is free. The STOP (P) and START (S) bits are
cleared from a reset or when the SSP module is disabled. Control of the I
when the P bit (SSPSTAT<4>) is set, or the bus is idle with both the S and P bits clear. When the
bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition
occurs.
In Multi-Master operation, the SDA line must be monitored to see if the signal level is the
expected output level. This check only needs to be done when a high level is output. If a high level
is expected and a low level is present, the device needs to release the SDA and SCL lines (set
the TRIS bits). There are two stages where this arbitration can be lost, they are:
• Address transfer
• Data transfer
When the slave logic is enabled, the slave continues to receive. If arbitration was lost during the
address transfer stage, communication to the device may be in progress. If addressed an ACK
pulse will be generated. If arbitration was lost during the data transfer stage, the device will need
to retransfer the data at a later time.
2
C slave mode will hold the SCL pin low when the CPU needs to respond
2
C bus may be taken when the P bit is set, or the bus is idle
1997 Microchip Technology Inc.
2
C bus may be taken
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