PIC16F876-04I/SP Microchip Technology, PIC16F876-04I/SP Datasheet - Page 286
![IC MCU FLASH 8KX14 EE 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC16F876-04I/SP
Manufacturer Part Number
PIC16F876-04I/SP
Description
IC MCU FLASH 8KX14 EE 28DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16C770-ISO.pdf
(8 pages)
4.PIC16F873-04SO.pdf
(218 pages)
5.PIC16F873-04SO.pdf
(5 pages)
6.PIC16F873-04SO.pdf
(5 pages)
Specifications of PIC16F876-04I/SP
Program Memory Type
FLASH
Program Memory Size
14KB (8K x 14)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
MSSP/PSP/USART
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
22
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
Minimum Operating Temperature
- 40 C
On-chip Adc
5-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16F873-04SO PDF datasheet #4
- PIC16F873-04SO PDF datasheet #5
- PIC16F873-04SO PDF datasheet #6
- Current page: 286 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
17.3.2
DS31017A-page 17-10
Enabling SPI I/O
The SSP consists of a transmit/receive Shift Register (SSPSR) and a buffer register (SSPBUF).
The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that
was written to the SSPSR, until the received data is ready. Once the 8-bits of data have been
received, that byte is moved to the SSPBUF register. Then the buffer full detect bit, BF
(SSPSTAT<0>), and the interrupt flag bit, SSPIF, are set. This double buffering of the received
data (SSPBUF) allows the next byte to start reception before reading the data that was just
received. Any write to the SSPBUF register during transmission/reception of data will be ignored,
and the write collision detect bit, WCOL (SSPCON1<7>), will be set. User software must clear
the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register com-
pleted successfully.
When the application software is expecting to receive valid data, the SSPBUF should be read
before the next byte of data to transfer is written to the SSPBUF. Buffer full bit, BF (SSPSTAT<0>),
indicates when SSPBUF has been loaded with the received data (transmission is complete).
When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally the SSP Interrupt is used to determine when the transmission/reception
has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to
be used, then software polling can be done to ensure that a write collision does not occur.
Example 17-1
Example 17-1:
The SSPSR is not directly readable or writable, and can only be accessed by addressing the
SSPBUF register. Additionally, the SSP status register (SSPSTAT) indicates the various status
conditions.
To enable the serial port, SSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or
reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCON registers, and then set the
SSPEN bit. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to
behave as the serial port function, some must have their data direction bits (in the TRIS register)
appropriately programmed. That is:
• SDI is automatically controlled by the SPI module
• SDO must have TRIS bit cleared
• SCK (Master mode) must have TRIS bit cleared
• SCK (Slave mode) must have TRIS bit set
• SS must have TRIS bit set
Any serial port function that is not desired may be overridden by programming the corresponding
data direction (TRIS) register to the opposite value.
LOOP BTFSS SSPSTAT, BF
BCF
BSF
GOTO
BCF
MOVF
MOVWF RXDATA
MOVF
MOVWF SSPBUF
STATUS, RP1
STATUS, RP0
LOOP
STATUS, RP0
SSPBUF, W
TXDATA, W
shows the loading of the SSPBUF (SSPSR) for data transmission.
Loading the SSPBUF (SSPSR) Register
Preliminary
;Specify Bank1
;
;Has data been received (transmit complete)?
;No
;Specify Bank0
;W reg = contents of SSPBUF
;Save in user RAM, if data is meaningful
;W reg = contents of TXDATA
;New data to xmit
1997 Microchip Technology Inc.
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