PIC24FJ192GA110-I/PT Microchip Technology, PIC24FJ192GA110-I/PT Datasheet - Page 20
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PIC24FJ192GA110-I/PT
Manufacturer Part Number
PIC24FJ192GA110-I/PT
Description
IC PIC MCU FLASH 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ128GA008-IPT.pdf
(12 pages)
2.PIC24FJ128GA106-IPT.pdf
(14 pages)
3.PIC24FJ128GA106-IPT.pdf
(330 pages)
4.PIC24FJ128GA106-IPT.pdf
(52 pages)
5.PIC24FJ128GB110-IPF.pdf
(292 pages)
Specifications of PIC24FJ192GA110-I/PT
Core Size
16-Bit
Program Memory Size
192KB (65.5K x 24)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Controller Family/series
PIC24
No. Of I/o's
85
Ram Memory Size
16KB
Cpu Speed
32MHz
No. Of Timers
5
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
85
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDMA240015 - BOARD MCV PIM FOR 24F256GADM240011 - KIT STARTER MPLAB FOR PIC24F MCU
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ192GA110-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC24FJ192GA110-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Configuration Words located in the test space. These
maintained to ensure device functionality, regardless of
Memory”, and reprogrammed to the desired value. It is
programmed from a ‘1’ to ‘0’ to enable code protection.
PIC24FJXXXGA1/GB1
3.7
Device configuration for PIC24FJXXXGA1/GB1 devices
is stored in Flash Configuration Words at the end of the
user space program memory, and in multiple register
registers reflect values read at any Reset from program
memory locations. The values for the Configuration
Words for the default device configurations are listed in
Table 3-6.
The values can be changed only by programming the
content of the corresponding Flash Configuration Word
and resetting the device. The Reset forces an automatic
reload of the Flash stored configuration values by
sequencing through the dedicated Flash Configuration
Words and transferring the data into the Configuration
registers.
For the PIC24FJXXXGA1/GB1 families, certain Config-
uration bits have default states that must always be
the settings of other Configuration bits. These bits and
their values are listed in Table 3-7.
To change the values of the Flash Configuration Word
once it has been programmed, the device must be Chip
Erased, as described in Section 3.5 “Erasing Program
not possible to program a ‘0’ to ‘1’, but they may be
TABLE 3-6:
TABLE 3-7:
DS39907A-page 20
Last Word
Last Word – 2
Last Word – 4
Note 1:
Address
Bit Location
CW2<2>
CW1<15>
CW1<10>
CW2<11>
Writing Configuration Words
This bit is implemented as I2C2SEL on
PIC24FJXXXGA110 devices, and should
be programmed as required.
(1)
DEFAULT CONFIGURATION
REGISTER VALUES
RESERVED CONFIGURATION
BIT LOCATIONS
Name
CW1
CW2
CW3
Value
Default Value
0
1
0
1
7FFFh
F7FFh
FFFFh
Table 3-8 shows the ICSP programming details for pro-
gramming the Configuration Word locations, including
the serial pattern with the ICSP command code which
must be transmitted, Least Significant bit first, using the
PGCx and PGDx pins (see Figure 3-2).
In Step 1, the Reset vector is exited. In Step 2, the
NVMCON register is initialized for programming of
code memory. In Step 3, the 24-bit starting destination
address for programming is loaded into the TBLPAG
register and W7 register.
The TBLPAG register must be loaded with the
following:
• 64 Kbyte devices: 00h
• 128, 192 and 256 Kbyte devices: 01h
To verify the data by reading the Configuration Words
after performing the write in order, the code protection
bits initially should be programmed to a ‘1’ to ensure
that the verification can be performed properly. After
verification is finished, the code protection bit can be
programmed to a ‘0’ by using a word write to the
appropriate Configuration Word.
© 2007 Microchip Technology Inc.