PIC16F874-04I/P Microchip Technology, PIC16F874-04I/P Datasheet - Page 74
![IC MCU FLASH 4KX14 EE 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC16F874-04I/P
Manufacturer Part Number
PIC16F874-04I/P
Description
IC MCU FLASH 4KX14 EE 40DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F873-04SO.pdf
(218 pages)
4.PIC16F873-04SO.pdf
(5 pages)
5.PIC16F873-04SO.pdf
(5 pages)
Specifications of PIC16F874-04I/P
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Oscillator Type
External
Core Processor
PIC
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC16F
No. Of I/o's
33
Eeprom Memory Size
128Byte
Ram Memory Size
192Byte
Cpu Speed
4MHz
No. Of
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
444-1001 - DEMO BOARD FOR PICMICRO MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F874-04I/PQ
Manufacturer:
Microchip Technology
Quantity:
10 000
Company:
Part Number:
PIC16F874-04I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F873-04SO PDF datasheet #3
- PIC16F873-04SO PDF datasheet #4
- PIC16F873-04SO PDF datasheet #5
- Current page: 74 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
4.3
DS31004A-page 4-6
1. MOVLW 55h
2. MOVWF PORTB
3. CALL SUB_1
4. BSF
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
Instruction Flow/Pipelining
PORTA, BIT3 (Forced NOP)
An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3, and Q4). Fetch takes one instruction
cycle while decode and execute takes another instruction cycle. However, due to Pipelining, each
instruction effectively executes in one cycle. If an instruction causes the program counter to
change (e.g. GOTO) then an extra cycle is required to complete the instruction
The instruction fetch begins with the program counter incrementing in Q1.
In the execution cycle, the fetched instruction is latched into the “Instruction Register (IR)” in
cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data
memory is read during Q2 (operand read) and written during Q4 (destination write).
Example 4-1
At time T
tion executes while the second instruction is fetched. During T
cutes while the third instruction is fetched. During T
third instruction (CALL SUB_1) is executed. When the third instruction completes execution, the
CPU forces the address of instruction four onto the Stack and then changes the Program Counter
(PC) to the address of SUB_1. This means that the instruction that was fetched during T
to be “flushed” from the pipeline. During T
the instruction at address SUB_1 is fetched. Finally during T
the instruction at address SUB_1 + 1 is fetched.
Example 4-1: Instruction Pipeline Flow
Fetch 1
CY
T
CY
0, the first instruction is fetched from program memory. During T
shows the operation of the two stage pipeline for the instruction sequence shown.
0
Execute 1
Fetch 2
T
CY
1
Execute 2
Fetch 3
T
CY
CY
2
4, instruction four is flushed (executed as a NOP) and
Execute 3
Fetch 4
CY
T
CY
3, the fourth instruction is fetched while the
3
CY
Fetch SUB_1 Execute SUB_1
5, instruction five is executed and
CY
Flush
T
2, the second instruction exe-
CY
1997 Microchip Technology Inc.
4
CY
Fetch SUB_1 + 1
1, the first instruc-
(Example
T
CY
CY
5
3 needs
4-1).
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