PIC18C252-I/SP Microchip Technology, PIC18C252-I/SP Datasheet - Page 61

• Manufacturer Part Number: PIC18C252-I/SP
• Description: IC MCU OTP 16KX16 A/D 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C252-I/SP

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 22
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 23
• Ram Memory Size: 1.5KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: MSSP, SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3DB18C452 - BOARD DAUGHTER ICEPIC3
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

5.2.3
The long write must be terminated by a RESET or any
interrupt.
The interrupt source must have its interrupt enable bit
set. When the source sets its interrupt flag, program-
ming will terminate. This will occur, regardless of the
settings of interrupt priority bits, the GIE/GIEH bit, or
the PIE/GIEL bit.
TABLE 5-2:
5.2.4
If a write is terminated by an unplanned event such as
loss of power, an unexpected RESET, or an interrupt
that was not disabled, the memory location just pro-
grammed should be verified and reprogrammed if
needed.
(default)
(default)
(default)
2001 Microchip Technology Inc.
GIEH
GIE/
X
X
0
0
1
0
1
INTERRUPTS
UNEXPECTED TERMINATION OF
WRITE OPERATIONS
(default)
(default)
(default)
GIEL
PIE/
X
X
0
1
0
1
0
LONG WRITE EXECUTION, INTERRUPT ENABLE BITS AND INTERRUPT RESULTS
high priority
high priority
(default)
(default)
Priority
low
low
X
X
X
1
0
0
1
Interrupt
(default)
Enable
0
1
1
1
1
1
1
Interrupt
Flag
X
0
1
1
1
1
1
Long write continues
even if interrupt flag becomes set.
Long write continues, will resume operations
when the interrupt flag is set.
Terminates long write, executes next instruction.
Terminates long write, executes next instruction.
Interrupt flag not cleared.
Terminates long write, executes next instruction.
Interrupt flag not cleared.
Terminates long write,
branches to low priority interrupt vector.
Interrupt flag can be cleared by ISR.
Terminates long write,
branches to high priority interrupt vector.
Interrupt flag can be cleared by ISR.
Interrupt flag not cleared.
Depending on the states of interrupt priority bits, the
GIE/GIEH bit or the PIE/GIEL bit, program execution
can either be vectored to the high or low priority Inter-
rupt Service Routine (ISR), or continue execution from
where programming commenced.
In either case, the interrupt flag will not be cleared
when programming is terminated and will need to be
cleared by the software.
Action
PIC18CXX2
DS39026C-page 59