PIC18LF2539-I/SO Microchip Technology, PIC18LF2539-I/SO Datasheet - Page 189
![IC MCU FLASH 12KX16 EE AD 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18LF2539-I/SO
Manufacturer Part Number
PIC18LF2539-I/SO
Description
IC MCU FLASH 12KX16 EE AD 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2439-ISO.pdf
(322 pages)
3.PIC18F2439-ISO.pdf
(6 pages)
4.PIC18F2439-ISO.pdf
(34 pages)
Specifications of PIC18LF2539-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
24KB (12K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1408 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1408 B
Interface Type
I2C, SPI, AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
16 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F2439-ISO PDF datasheet #2
- PIC18F2439-ISO PDF datasheet #3
- PIC18F2439-ISO PDF datasheet #4
- Current page: 189 of 322
- Download datasheet (7Mb)
18.4
Figure 18-3 shows the operation of the A/D converter
after the GO bit has been set. Clearing the GO/DONE
bit during a conversion will abort the current conver-
sion. The A/D result register pair will NOT be updated
with the partially completed A/D conversion sample.
That is, the ADRESH:ADRESL registers will continue
to contain the value of the last completed conversion
FIGURE 18-3:
18.4.1
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16-bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
FIGURE 18-4:
2002 Microchip Technology Inc.
A/D Conversions
T
CY
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
A/D RESULT REGISTERS
- T
AD
7
Conversion Starts
0000 00
ADRESH
T
b9
AD
A/D CONVERSION T
A/D RESULT JUSTIFICATION
1 T
Right Justified
AD
b8
2 1 0 7
ADFM = 1
2 T
AD
b7
10-bit Result
3 T
ADRESL
AD
b6
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
4 T
AD
AD
b5
0
5 T
CYCLES
Preliminary
ADIF bit is set, holding capacitor is connected to analog input.
10-bit Result
AD
b4
6 T
AD
b3
7 T
(or the last value written to the ADRESH:ADRESL reg-
isters). After the A/D conversion is aborted, a 2 T
is required before the next acquisition is started. After
this 2 T
automatically started. The GO/DONE bit can then be
set to start the conversion.
Format Select bit (ADFM) controls this justification.
Figure 18-4 shows the operation of the A/D result justi-
fication. The extra bits are loaded with ‘0’s. When an
A/D result will not overwrite these locations (A/D
disable), these registers may be used as two general
purpose 8-bit registers.
Note:
AD
b2
7
8
AD
ADRESH
T
AD
wait, acquisition on the selected channel is
b1
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
10-bit Result
9 T
AD
ADFM = 0
b0
Left Justified
10
0 7 6 5
PIC18FXX39
T
AD
b0
ADRESL
11
0000 00
DS30485A-page 187
0
AD
wait
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