PIC16F877-20/P Microchip Technology, PIC16F877-20/P Datasheet - Page 89
![IC MCU FLASH 8KX14 EE 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC16F877-20/P
Manufacturer Part Number
PIC16F877-20/P
Description
IC MCU FLASH 8KX14 EE 40DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16C770-ISO.pdf
(8 pages)
4.PIC16F873-04SO.pdf
(218 pages)
5.PIC16F873-04SO.pdf
(5 pages)
6.PIC16F873-04SO.pdf
(5 pages)
Specifications of PIC16F877-20/P
Core Size
8-Bit
Program Memory Size
14KB (8K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC16F
No. Of I/o's
33
Eeprom Memory Size
256Byte
Ram Memory Size
368Byte
Cpu Speed
20MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
444-1001 - DEMO BOARD FOR PICMICRO MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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9.2.14
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sam-
pled low, the baud rate generator is reloaded and
counts down to 0. When the baud rate generator times
out, the SCL pin will be brought high, and one T
(baud rate generator rollover count) later, the SDA pin
will be de-asserted. When the SDA pin is sampled high
FIGURE 9-17:
2001 Microchip Technology Inc.
STOP CONDITION TIMING
SCL
SDA
Note: T
Write to SSPCON2
Falling edge of
9th clock
BRG
STOP CONDITION RECEIVE OR TRANSMIT MODE
ACK
= one baud rate generator period.
Set PEN
SDA asserted low before rising edge of clock
to setup STOP condition
T
T
BRG
BRG
BRG
T
SCL brought high after T
BRG
SCL = 1 for T
after SDA sampled high. P bit (SSPSTAT<4>) is set.
P
T
BRG
while SCL is high, the P bit (SSPSTAT<4>) is set. A
T
set (Figure 9-17).
Whenever the firmware decides to take control of the
bus, it will first determine if the bus is busy by checking
the S and P bits in the SSPSTAT register. If the bus is
busy, then the CPU can be interrupted (notified) when
a STOP bit is detected (i.e., bus is free).
9.2.14.1
If the user writes the SSPBUF when a STOP sequence
is in progress, then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
BRG
BRG
PEN bit (SSPCON2<2>) is cleared by
later, the PEN bit is cleared and the SSPIF bit is
hardware and the SSPIF bit is set
, followed by SDA = 1 for T
BRG
WCOL Status Flag
PIC16F87X
BRG
DS30292C-page 87