PIC32MX440F256H-80I/PT Microchip Technology, PIC32MX440F256H-80I/PT Datasheet - Page 22
![IC PIC MCU FLASH 256K 64-TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC32MX440F256H-80I/PT
Manufacturer Part Number
PIC32MX440F256H-80I/PT
Description
IC PIC MCU FLASH 256K 64-TQFP
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.MA320002.pdf
(208 pages)
2.DM320001.pdf
(44 pages)
3.PIC32MX320F032H-40IPT.pdf
(48 pages)
4.PIC32MX320F032H-40IPT.pdf
(66 pages)
5.PIC32MX320F032H-40IPT.pdf
(22 pages)
6.PIC32MX460F256L-80IPT.pdf
(632 pages)
7.PIC32MX320F064H-40IMR.pdf
(172 pages)
Specifications of PIC32MX440F256H-80I/PT
Program Memory Type
FLASH
Program Memory Size
256KB (256K x 8)
Package / Case
64-TFQFP
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C , SPI , UART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
51
Number Of Timers
5 x 16 bit, 1 x 32 bit
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
PIC32
Ram Memory Size
32KB
Cpu Speed
80MHz
No. Of Timers
5
Embedded Interface Type
EUSART, I2C, SPI, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX440F256H-80I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC32MX440F256H-80I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC32MX3XX/4XX
3.2
The PIC32MX3XX/4XX Family core contains several
logic blocks working together in parallel, providing an
efficient high performance computing engine. The fol-
lowing blocks are included with the core:
• Execution Unit
• Multiply/Divide Unit (MDU)
• System Control Coprocessor (CP0)
• Fixed Mapping Translation (FMT)
• Dual Internal Bus interfaces
• Power Management
• MIPS16e Support
• Enhanced JTAG (EJTAG) Controller
3.2.1
The PIC32MX3XX/4XX Family core execution unit
implements a load/store architecture with single-cycle
ALU operations (logical, shift, add, subtract) and an
autonomous multiply/divide unit. The core contains
thirty-two 32-bit general purpose registers used for
integer operations and address calculation. One addi-
tional register file shadow set (containing thirty-two reg-
isters) is added to minimize context switching overhead
during interrupt/exception processing. The register file
consists of two read ports and one write port and is fully
bypassed to minimize operation latency in the pipeline.
• 32-bit adder used for calculating the data address
• Address unit for calculating the next instruction
• Logic for branch determination and branch target
• Load aligner
• Bypass multiplexers used to avoid stalls when
• Leading Zero/One detect unit for implementing the
• Arithmetic Logic Unit (ALU) for performing bitwise
• Shifter and Store Aligner
DS61143F-page 20
The execution unit includes:
address
address calculation
executing
producing instructions are followed closely by
consumers of their results
CLZ and CLO instructions
logical operations
Architecture Overview
EXECUTION UNIT
instructions
streams
where
data
Preliminary
3.2.2
The PIC32MX3XX/4XX Family core includes a multi-
ply/divide unit (MDU) that contains a separate pipeline
for multiply and divide operations. This pipeline oper-
ates in parallel with the integer unit (IU) pipeline and
does not stall when the IU pipeline stalls. This allows
MDU operations to be partially masked by system stalls
and/or other integer unit instructions.
The high-performance MDU consists of a 32x16 booth
recoded multiplier, result/accumulation registers (HI
and LO), a divide state machine, and the necessary
multiplexers and control logic. The first number shown
(‘32’ of 32x16) represents the rs operand. The second
number (‘16’ of 32x16) represents the rt operand. The
PIC32MX core only checks the value of the latter (rt)
operand to determine how many times the operation
must pass through the multiplier. The 16x16 and 32x16
operations pass through the multiplier once. A 32x32
operation passes through the multiplier twice.
The MDU supports execution of one 16x16 or 32x16
multiply operation every clock cycle; 32x32 multiply
operations can be issued every other clock cycle.
Appropriate interlocks are implemented to stall the
issuance of back-to-back 32x32 multiply operations.
The multiply operand size is automatically determined
by logic built into the MDU.
Divide operations are implemented with a simple 1 bit
per clock iterative algorithm. An early-in detection
checks the sign extension of the dividend (rs) operand.
If rs is 8 bits wide, 23 iterations are skipped. For a 16-
bit-wide rs, 15 iterations are skipped, and for a 24-bit-
wide rs, 7 iterations are skipped. Any attempt to issue
a subsequent MDU instruction while a divide is still
active causes an IU pipeline stall until the divide oper-
ation is completed.
Table 3-1 lists the repeat rate (peak issue rate of cycles
until the operation can be reissued) and latency (num-
ber of cycles until a result is available) for the PIC32MX
core multiply and divide instructions. The approximate
latency and repeat rates are listed in terms of pipeline
clocks.
MULTIPLY/DIVIDE UNIT (MDU)
© 2009 Microchip Technology Inc.