ATMEGA1284P-AU Atmel, ATMEGA1284P-AU Datasheet - Page 306
![MCU AVR 128K ISP FLASH 44-TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA1284P-AU
Manufacturer Part Number
ATMEGA1284P-AU
Description
MCU AVR 128K ISP FLASH 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA644PA-PU.pdf
(581 pages)
2.ATMEGA644PA-PU.pdf
(32 pages)
3.ATMEGA1284PR231-AU.pdf
(380 pages)
Specifications of ATMEGA1284P-AU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRAVEN, ATAVRRZUSBSTICK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
44TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Rom Size
4 KB
Height
1.05 mm
Length
10.1 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Width
10.1 mm
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
4KB
Ram Memory Size
16KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA1284P-AU
Manufacturer:
ATMEL
Quantity:
1 000
Company:
Part Number:
ATMEGA1284P-AU
Manufacturer:
ATMEL
Quantity:
748
Part Number:
ATMEGA1284P-AU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 306 of 380
- Download datasheet (7Mb)
25.8
25.8.1
8059D–AVR–11/09
Serial Downloading
Serial Programming Pin Mapping
Both the Flash and EEPROM memory arrays can be programmed using a serial programming
bus while RESET is pulled to GND. The serial programming interface consists of pins SCK,
MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction
needs to be executed first before program/erase operations can be executed. NOTE, in
25-15 on page
SPI pins dedicated for the internal Serial Peripheral Interface - SPI.
Table 25-15. Pin Mapping Serial Programming
Figure 25-10. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
Symbol
MOSI
MISO
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
2. V
SCK
XTAL1 pin.
CC
- 0.3V < AVCC < V
306, the pin mapping for serial programming is listed. Not all packages use the
(PDIP-40)
Pins
PB5
PB6
PB7
MOSI
MISO
SCK
ck
ck
CC
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
+ 0.3V, however, AVCC should always be within 1.8 - 5.5V
XTAL1
RESET
GND
(TQFP-44)
(1)
Pins
PB5
PB6
PB7
AVCC
VCC
+1.8 - 5.5V
+1.8 - 5.5V
I/O
O
I
I
(2)
ATmega1284P
ck
ck
>= 12 MHz
>= 12 MHz
Serial Data out
Serial Data in
Description
Serial Clock
Table
306
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